Work

5. 4 GOPS, 81 GB/s Linear Array Architecture DSP

Year: 1998

Type: article

Source: IEICE Transactions on Electronics

Authors: A. Hashiguchi, M. Kurokawa, Kenichiro Nakamura, Hiroshi Okuda, K. Aoyama, Mitsuharu Ohki, K. Seno, Ichiro Kumata, Masatoshi Aikawa, H. Hanaki, Takao Yamazaki, Mitsuo Soneda, Seiichiro Iwase

Language: English

Topic: Parallel Computing and Optimization Techniques

Subfield: Hardware and Architecture

Field: Computer Science

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W185855432

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Cited by: 2

Related to: 10