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Author

K. Seno

Institution: Sony (Japan)
OpenAlex ID: A5111496580
Dynamic voltage and frequency management for a low-power embedded microprocessor
2005 · M. Nakai, S. Akui, et al. · IEEE Journal of Solid-State Circuits · 182
Dynamic voltage and frequency management for a low-power embedded microprocessor
2004 · S. Akui, K. Seno, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 37
A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier
1993 · K. Seno, K. Knorpp, et al. · IEEE Journal of Solid-State Circuits · 27
Heterogeneous reconfigurable systems
2002 · J.M. Rabaey, A. Abnous, et al. · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · 26
A 9 ns 16 Mb CMOS SRAM with offset reduced current sense amplifier
1993 · K. Seno, K. Knorpp, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 19
A 2.2 GOPS video DSP with 2-RISC MIMD, 6-PE SIMD architecture for real-time MPEG2 video coding/decoding
2002 · E. Iwata, K. Seno, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 12
5.4 GOPS linear array architecture DSP for video-format conversion
2002 · M. Kurokawa, A. Hashiguchi, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 7
5. 4 GOPS, 81 GB/s Linear Array Architecture DSP
1998 · A. Hashiguchi, M. Kurokawa, et al. · IEICE Transactions on Electronics · 2
A multibit test trigger circuit for megabit SRAMs
1990 · F. Miyaji, T. Emori, et al. · IEEE Journal of Solid-State Circuits · 2
FP 15.7: 5.4GOPS Linear Array Architecture DSP for Video-Format Conversion
1996 · M. Kurokawa, A. Hashiguchi, et al. · 1
A parametric DCT macro cell generator with a simulation model and an accuracy report
2002 · M. Ohki, T. Nagai, et al. · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems
A 2.2 GOPS video DSP for real-time MPEG2 video coding/decoding
1997 · Ichiro Kumata, Eiji Iwata, et al. · 電子情報通信学会技術研究報告. ICD, 集積回路
実時間mpeg2ビデオ符号化・復号化用の2‐risc Mimd,6‐pe Simdアーキテクチャを備えた2.2gopsビデオdsp
1997 · Eiji Iwata, K. Seno, et al.
Isscc 93 I Session 16 / Static Memories I Paper Fa 16.4
1993 · K. Seno, Kurt Knorpp, et al.
Works count: 14
Citation count: 315
H-index: 7
I10-index: 6
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