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Ken Matthews

Observed name: K. Matthews
Observed institution: Ames Research Center
OpenAlex ID: A5021189444
Comparison of effective work function extraction methods using capacitance and current measurement techniques
2006 · Huang-Chun Wen, Rino Choi, et al. · IEEE Electron Device Letters · 40
STLM: A Sidewall TLM Structure for Accurate Extraction of Ultralow Specific Contact Resistivity
2013 · Kausik Majumdar, Saikumar Vivekanand, et al. · IEEE Electron Device Letters · 22
Effective Schottky Barrier Height modulation using dielectric dipoles for source/drain specific contact resistivity improvement
2012 · K.-W. Ang, K. Majumdar, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 17
Mapping Defect Density in MBE Grown ${\rm In}_{0.53}{\rm Ga}_{0.47}{\rm As}$ Epitaxial Layers on Si Substrate Using Esaki Diode Valley Characteristics
2014 · Kausik Majumdar, Paul Thomas, et al. · IEEE Transactions on Electron Devices · 13
Statistical demonstration of silicide-like uniform and ultra-low specific contact resistivity using a metal/high-k/Si stack in a sidewall contact test structure
2014 · K. Majumdar, R. Clark, et al. · Symposium on VLSI Technology · 11
Investigation of negative bias temperature instability dependence on fin width of silicon-on-insulator-fin-based field effect transistors
2015 · Chadwin D. Young, Arnost Neugroschel, et al. · Journal of Applied Physics · 9
Silicon Superlattice on SOI for High Mobility and Reduced Leakage
2007 · Robert J. Mears, Marek Hytha, et al. · IEEE International SOI Conference (SOI) · 8
VLSI processed InGaAs on Si MOSFETs with thermally stable, self-aligned Ni-InGaAs contacts achieving: Enhanced drive current and pathway towards a unified contact module
2013 · Rinus T. P. Lee, R. J. W. Hill, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 7
Novel resist approaches to enable EUV lithography in high volume manufacturing and extensions to future nodes
2015 · Mark Neisser, Kevin Cummings, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 5
Ultra low contact resistivity (< 1×10−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III–V fin TLM structure fabricated with III–V on Si substrates
2014 · Rinus T.P. Lee, Y. Ohsawa, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 3
Three-dimensional columnar optical nanostructures fabricated by using lithography-free templating approach
2004 · Hou T. Ng, K. Matthews, et al. · Applied Physics Letters · 3
(Invited) Passivation Schemes for Ge High-K Metal Gate MOSFETs on Si for VLSI Production
2014 · Kandabara Tapily, Tat Ngai, et al. · ECS Transactions · 2
Contact resistance improvement by dielectric breakdown in semiconductor-dielectric-metal contact
2013 · Kausik Majumdar, Chris Hobbs, et al. · Applied Physics Letters · 2
(Invited) Electrical Characterization and Reliability Assessment of Double-Gate FinFETs
2013 · Chadwin D Young, Kerem Akarvardar, et al. · ECS Transactions · 2
A merged MuGFET and planar SOI process
2007 · Andrew Marshall, C. Rinn Cleavelin, et al. · IEEE International SOC Conference (SOCC) · 1
Effects of Temperature on Metal Gate FinFET Circuit Performance
2006 · Andrew Marshall, Weize Xiong, et al. · IEEE International SOI Conference (SOI) · 1
(Invited) Passivation Schemes for Ge High-K Metal Gate MOSFETs on Si for VLSI Production
2014 · Kandabara Tapily, Tat Ngai, et al. · ECS Meeting Abstracts
Electrical Characterization and Reliability Assessment of Double-gate FinFETs
2012 · Chadwin D. Young, Kerem Akarvardar, et al. · ECS Meeting Abstracts
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Works count: 19
Citation count: 146
H-index: 7
I10-index: 5
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