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Sam-Young Bang

Observed name: Samyoung Bang
OpenAlex ID: A5023023936
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion
2008 · Seung-Jun Bae, Kwang-Il Park, et al. · IEEE Journal of Solid-State Circuits · 66
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques
2008 · Seung-Jun Bae, Young-Soo Sohn, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 47
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking
2018 · Young-Ju Kim, Hye-Jung Kwon, et al. · IEEE Journal of Solid-State Circuits · 41
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction
2010 · Tae-Young Oh, Young-Soo Sohn, et al. · IEEE Journal of Solid-State Circuits · 34
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW
2011 · Seung-Jun Bae, Young-Soo Sohn, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 33
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking
2018 · Young-Ju Kim, Hye-Jung Kwon, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 28
A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface
2010 · Seung-Jun Bae, Young-Soo Sohn, et al. · Symposium on VLSI Circuits · 15
An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion
2007 · Jeong-Don Ihm, Seung-Jun Bae, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 14
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction
2010 · Tae-Young Oh, Young-Soo Sohn, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 9
Clock clustering and IO optimization for 3D integration
2015 · Samyoung Bang, Kwangsoo Han, et al. · International Workshop on System Level Interconnect Prediction (SLIP) · 6
Delay uncertainty and signal criticality driven routing channel optimization for advanced DRAM products
2016 · Samyoung Bang, Kwangsoo Han, et al. · Asia and South Pacific Design Automation Conference (ASP-DAC) · 4
2.5nsバンクツーバンクアクティブ時間を持ちバンクグループ制限の無い7Gb/s/pin GDDR5 SDRAM
2010 · Tae-Young Oh, Young-Soo Sohn, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Works count: 12
Citation count: 297
H-index: 9
I10-index: 8
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