A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction
Year: 2010
Type: conference-paper
Authors: Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seok-Won Hwang, Jeong-Don Lim, Kwang-Il Park, Joo Sun Choi, Young-Hyun Jun
Institutions: Samsung (South Korea), Samsung Electronics (South Korea)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W4249944618