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Cheol-Goo Park

OpenAlex ID: A5035429565
A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques
2008 · Seung-Jun Bae, Young-Soo Sohn, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 47
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction
2010 · Tae-Young Oh, Young-Soo Sohn, et al. · IEEE Journal of Solid-State Circuits · 34
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW
2011 · Seung-Jun Bae, Young-Soo Sohn, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 33
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction
2010 · Tae-Young Oh, Young-Soo Sohn, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 9
2.5nsバンクツーバンクアクティブ時間を持ちバンクグループ制限の無い7Gb/s/pin GDDR5 SDRAM
2010 · Tae-Young Oh, Young-Soo Sohn, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference
Works count: 5
Citation count: 123
H-index: 4
I10-index: 3
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