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Author

J. P. Norum

Observed names: J. Norum, J.P. Norum
Institution: IBM (United States)
OpenAlex ID: A5024672595
High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography
2006 · P. Agnello, T. Ivers, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 115
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL
2012 · S. Narasimha, P. Chang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 95
Embedded DRAM: Technology platform for the Blue Gene/L chip
2005 · S. S. Iyer, J. E. Barth, et al. · IBM Journal of Research and Development · 76
45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications
2011 · S. S. Iyer, G. Freeman, et al. · IBM Journal of Research and Development · 20
A 0.127 μm2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications
2006 · G. Wang, K. Cheng, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 14
0.026µm2 high performance Embedded DRAM in 22nm technology for server and SOC applications
2014 · C. Pei, G. Wang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 5
Performance-optimized gate-first 22-nm SOI technology with embedded DRAM
2015 · G. Freeman, P. Chang, et al. · IBM Journal of Research and Development · 4
22nm technology yield optimization using multivariate 3D virtual fabrication
2013 · B. Cipriany, B. Jagannathan, et al. · International Conference on Simulation of Semiconductor Processes and Devices · 4
Trimming of hard-masks by gaseous Chemical Oxide Removal (COR) for sub-10 nm gates/fins, for gate length control and for embedded logic
2004 · W.C. Natzle, D. Horak, et al. · ASMC proceedings · 4
Comparison of Effects of Ionizing Radiation and High-Current Stress on Characteristics of Self-Aligned Bipolar Transistors
1988 · T. C. Chen, J. P. Norum, et al. · International Conference on Solid State Devices and Materials (SSDM) · 4
A 0.168μm/sup 2/0.11μm/sup 2/ highly scalable high performance embedded DRAM cell for 90/65-nm logic applications
2005 · G. Wang, P. Parries, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 3
A 0.13 μm logic-based embedded DRAM technology with electrical fuses, Cu interconnect in SiLK/sup TM/, sub-7 ns random access time and its extension to the 0.10 μm generation
2002 · V. Klee, J. Norum, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 2
A 0.168pm2/0.1 1pm2 Highly Scatable High Performance embedded DRAM Cell for 90165-nm Logic Applications
2004 · G. Wang, P. Parries, et al.
Works count: 13
Citation count: 346
H-index: 5
I10-index: 5
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