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C. Schiller

Observed names: C.E. Schiller, Carl E. Schiller, Carl Schiller
OpenAlex ID: A5029325812
A 7nm CMOS technology platform for mobile and high performance compute application
2017 · S. Narasimha, B. Jagannathan, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 62
Scaling of 32nm low power SRAM with high-K metal gate
2008 · H. S. Yang, R. Wong, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 53
A 0.25 μm CMOS SOI technology and its application to 4 Mb SRAM
2002 · D.J. Schepis, F. Assaderaghi, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 51
A 4-GHz 8-b ADC system
1991 · C. Schiller, P. Byrne · IEEE Journal of Solid-State Circuits · 31
Case studies of fault isolation for the global failing patterns on SRAM bitmap caused by the defects in peripheral logic regions
2013 · Jianhua Yin, Jian Yu, et al. · ASMC proceedings · 13
Tristate Inverter Array: A new test structure that compliments traditional SRAM arrays as a yield learning vehicle
2014 · Ishtiaq Ahsan, Carl Schiller, et al. · ASMC proceedings · 6
Tristate Inverter Array: A New Technology Development Yield Learning Vehicle Complementing Traditional SRAM Arrays
2015 · Ishtiaq Ahsan, Carl Schiller, et al. · IEEE Transactions on Semiconductor Manufacturing · 5
A simple and high-performance 130 nm SOI eDRAM technology using floating-body pass-gate transistor in trench-capacitor cell for system-on-a-chip (SoC) applications
2004 · M. Kumar, M.D. Steigerwalt, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 4
Works count: 8
Citation count: 225
H-index: 6
I10-index: 5
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