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Author

Stefan Cosemans

Observed names: Cosemans, Stefan, S Cosemans, S. Cosemans
Institution: IMEC
Observed institutions: IMEC, KU Leuven
OpenAlex ID: A5031630779
Spin-Hall-assisted magnetic random access memory
2014 · A. van den Brink, S. Cosemans, et al. · Applied Physics Letters · 121
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DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC
2022 · Kodai Ueyoshi, Ioannis A. Papistas, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 96
SOT-MRAM Based Analog in-Memory Computing for DNN Inference
2020 · J. Doevenspeck, K. Garello, et al. · Symposium on VLSI Technology · 92
Dynamic ‘hour glass’ model for SET and RESET in HfO2 RRAM
2012 · R. Degraeve, A. Fantini, et al. · Symposium on VLSI Technology · 89
Towards 10000TOPS/W DNN Inference with Analog in-Memory Computing – A Circuit Blueprint, Device Options and Requirements
2019 · S. Cosemans, B. Verhoef, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 71
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Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators
2021 · Hongwu Jiang, Wantong Li, et al. · IEEE Design and Test · 64
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A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node
2021 · Mohit Kumar Gupta, Pieter Weckx, et al. · IEEE Transactions on Electron Devices · 58
One-Selector One-Resistor Cross-Point Array With Threshold Switching Selector
2015 · Leqi Zhang, Stefan Cosemans, et al. · IEEE Transactions on Electron Devices · 55
The VO2 interface, the metal-insulator transition tunnel junction, and the metal-insulator transition switch On-Off resistance
2012 · K. Martens, I. P. Radu, et al. · Journal of Applied Physics · 54
Design and benchmarking of hybrid CMOS-Spin Wave Device Circuits compared to 10nm CMOS
2015 · Odysseas Zografos, Bart Soree, et al. · IEEE International Conference on Nanotechnology (IEEE-NANO) · 53
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Hourglass concept for RRAM: A dynamic and statistical device model
2014 · R. Degraeve, A. Fantini, et al. · IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) · 51
Analysis of vertical cross-point resistive memory (VRRAM) for 3D RRAM design
2013 · Leqi Zhang, Stefan Cosemans, et al. · IEEE International Memory Workshop (IMW) · 48
The Complementary FET (CFET) 6T-SRAM
2021 · Mohit Kumar Gupta, Pieter Weckx, et al. · IEEE Transactions on Electron Devices · 47
A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers
2009 · Stefan Cosemans, Wim Dehaene, et al. · IEEE Journal of Solid-State Circuits · 46
A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm 2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration
2021 · I. A. Papistas, Stefan Cosemans, et al. · Custom Integrated Circuits Conference · 45
A Low-Power Embedded SRAM for Wireless Applications
2007 · S. Cosemans, W. Dehaene, et al. · IEEE Journal of Solid-State Circuits · 43
Selector design considerations and requirements for 1 SIR RRAM crossbar array
2014 · Leqi Zhang, Stefan Cosemans, et al. · IEEE International Memory Workshop (IMW) · 40
High-drive current (>1MA/cm2) and highly nonlinear (>103) TiN/amorphous-Silicon/TiN scalable bidirectional selector with excellent reliability and its variability impact on the 1S1R array performance
2014 · Leqi Zhang, Bogdan Govoreanu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 38
11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge
2024 · Pascal Alexander Hager, Bert Moons, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 32
A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy
2011 · Vibhu Sharma, Stefan Cosemans, et al. · IEEE Journal of Solid-State Circuits · 31
Time and workload dependent device variability in circuit simulations
2011 · D. Rodopoulos, S. B. Mahato, et al. · IEEE International Conference on IC Design and Technology (ICICDT) · 31
A 3.6pJ/access 480MHz, 128Kbit on-Chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability
2008 · Stefan Cosemans, Wim Dehaene, et al. · European Solid-State Circuits Conference (ESSCIRC) · 31
Opportunities and Limitations of Emerging Analog in-Memory Compute DNN Architectures
2020 · Pouya Houshmand, Stefan Cosemans, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 30
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IGZO-Based Compute Cell for Analog In-Memory Computing—DTCO Analysis to Enable Ultralow-Power AI at Edge
2020 · D. Saito, J. Doevenspeck, et al. · IEEE Transactions on Electron Devices · 30
STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application
2021 · S. Rao, W. Kim, et al. · IEEE International Memory Workshop (IMW) · 27
Works count: 98
Citation count: 1,971
H-index: 26
I10-index: 56
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