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Diksha Shekhawat

Modeling, hardware architecture, and performance analyses of an AEAD-based lightweight cipher
2024 · Kartik Jhawar, Jugal Gandhi, et al. · Journal of Real-Time Image Processing · 10
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A Hardware Generator for Posit Arithmetic and its FPGA Prototyping
2021 · Diksha Shekhawat, Apoorva Jangir, et al. · International Symposium on VLSI Design and Test (VDAT) · 7
GAN4IP: A unified GAN and logic locking-based pipeline for hardware IP security
2024 · Jugal Gandhi, Diksha Shekhawat, et al. · Sadhana · 6
An FPGA Prototyping of the GIFT Cipher for Image Security Applications
2021 · Apoorva Jangir, Diksha Shekhawat, et al. · 5
Security Evaluation of Lightweight SBoxes
2023 · Jugal Gandhi, Diksha Shekhawat, et al. · IEEE International Symposium on Smart Electronic Systems (iSES) · 4
LOKI: A Secure FPGA Prototyping of IoT IP with Lightweight Logic Locking
2023 · Jugal Gandhi, Diksha Shekhawat, et al. · IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) · 4
A time domain 2D OaA-based convolutional neural networks accelerator
2023 · Rudresh Pratap Singh, Shreyam Kumar, et al. · Memories - Materials Devices Circuits and Systems · 4
Emerging Frontiers and Limitations of Logic Locking for Secure IC Design
2024 · Jugal Gandhi, Diksha Shekhawat, et al. · IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) · 3
PHAc: Posit Hardware Accelerator for Efficient Arithmetic Logic Operations
2023 · Diksha Shekhawat, Jugal Gandhi, et al. · Lecture notes in computer science · 3
A NAND Flash Memory Controller for Energy-Constrained Edge Computing Applications
2024 · Diksha Shekhawat, Jugal Gandhi, et al. · Lecture notes in electrical engineering · 2
LightLock: Ensuring Hardware IP Security in IoT Environment with Lightweight Logic Locking
2024 · Jugal Gandhi, Diksha Shekhawat, et al. · Lecture notes in electrical engineering · 2
A Low-overhead Dilithium-NTT Architecture using Accelerated K-RED Modular Reduction Unit
2026 · Harsh Gupta, Aryan Goyal, et al. · International Symposium on Quality Electronic Design (ISQED) · 1
Fast-Track Functional Verification Framework for Next-Generation IP Cores
2025 · Anirban Nayak, Jugal Gandhi, et al. · IEEE International Symposium on Smart Electronic Systems (iSES) · 1
SHAKTI: Securing Hardware IPs by Cascade Gated Multiplexer-Based Logic Obfuscation
2025 · Jugal Gandhi, Nikhil Handa, et al. · International Conference on VLSI Design · 1
KAVACH: A CAD-based bit-flip obfuscation framework for hardware integrity protection
2026 · Jugal Gandhi, Nikhil Handa, et al. · Computers & Security
Functional obfuscation of lightweight crypto cores for improved security against IP piracy
2026 · Jugal Gandhi, Diksha Shekhawat, et al. · The Journal of Supercomputing
A Unified UVM Framework for Accelerated Verification of Block Cipher IP Cores
2026 · Harsh Singh, Diksha Shekhawat, et al. · International Symposium on VLSI Design and Test (VDAT)
A UVMF-Based Security-Aware Functional Verification Framework for AES-256 Hardware IP
2026 · Ayush Modi, Diksha Shekhawat, et al. · International Symposium on VLSI Design and Test (VDAT)
A RISC-V SoC with an Integrated CORDIC Coprocessor for Improved Trigonometric Efficiency
2025 · Vaibhav Malik, Vipul Bansal, et al. · IEEE International Symposium on Smart Electronic Systems (iSES)
An HLS-driven Architectural Design for the PRESENT Lightweight Block Cipher
2025 · Atul M., Diksha Shekhawat, et al. · IEEE International Conference on Public Key Infrastructure and its Applications (PKIA)
Works count: 20
Citation count: 53
H-index: 4
I10-index: 1
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