A UVMF-Based Security-Aware Functional Verification Framework for AES-256 Hardware IP
Year: 2026
Type: conference-paper
Abstract: Advanced Encryption Standard (AES-256) is widely used for secure data communication. The verification of AES-256 hardware IP cores is crucial to ensure both functional accuracy and security robustness. This paper presents a securityaware functional verification framework for an AES-256 intellectual property (IP) using the Universal Verification Methodology Framework (UVMF). The proposed framework integrates constrained-random stimulus generation, protocol-aware monitoring, scoreboard-based comparison, functional coverage, and SystemVerilog Assertions (SVA). The verification environment evaluates the black-box AES-256 IP under various test scenarios, including directed test vectors, random vectors, boundary conditions, and corner cases. In addition to traditional functional verification, the framework also incorporates security-aware verification strategies. Various security-oriented test patterns, such as walking-bit, symmetry-bit, avalanche-effect analysis, and stuck-at fault conditions, are applied to assess the robustness of IP. The proposed work achieves$\mathbf{1 0 0 \%}$functional and assertion coverage for the verification scenarios. Experimental results show effective bug detection with improved verification efficiency. The outcomes demonstrate the high functional coverage and robust security of the AES-256 IP. The proposed methodology provides a systematic, scalable approach to security-aware verification of cryptographic hardware using UVMF.
Language: English
Subfield: Artificial Intelligence
Field: Computer Science
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W7220706166