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B.-Y. Nguyen

Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond
2010 · F. Andrieu, O. Weber, et al. · Symposium on VLSI Technology · 109
Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs
2012 · M. A. Karim, Y. S. Chauhan, et al. · IEEE Electron Device Letters · 55
A Self-Rectifying $\hbox{AlO}_{y}$ Bipolar RRAM With Sub-50-$\mu\hbox{A}$ Set/Reset Current for Cross-Bar Architecture
2012 · X. A. Tran, W. Zhu, et al. · IEEE Electron Device Letters · 53
Self-Selection Unipolar $\hbox{HfO}_{x}$ -Based RRAM
2012 · X. A. Tran, W. Zhu, et al. · IEEE Transactions on Electron Devices · 35
Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below
2009 · C. Fenouillet-Beranger, P. Perreau, et al. · European Solid-State Device Research Conference · 34
Performance and Variability Comparisons between Multi-Gate FETs and Planar SOI Transistors
2006 · A. V-Y Thean, Z-H Shi, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 34
Self-rectifying and forming-free unipolar HfOx based-high performance RRAM built by fab-avaialbe materials
2011 · X.A. Tran, B. Gao, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 29
Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below
2009 · C. Fenouillet-Beranger, P. Perreau, et al. · European Solid-State Circuits Conference (ESSCIRC) · 29
Strain distribution in a transistor using self-assembled SiGe islands in source and drain regions
2006 · G. S. Kar, S. Kiravittaya, et al. · Applied Physics Letters · 26
Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections
2022 · A. Vandooren, N. Parihar, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 23
A novel low-voltage biasing scheme for double gate FBC achieving 5s retention and 1016 endurance at 85°C
2010 · Z. Lu, N. Collaert, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 23
Novel nanostructure architectures
2004 · O.G. Schmidt, A. Rastelli, et al. · Physica E Low-dimensional Systems and Nanostructures · 23
Analysis of sense margin and reliability of 1T-DRAM fabricated on thin-film UTBOX substrates
2009 · N. Collaert, M. Aoulaiche, et al. · IEEE International SOI Conference (SOI) · 22
Ni Electrode Unipolar Resistive RAM Performance Enhancement by $\hbox{AlO}_{y}$ Incorporation Into $\hbox{HfO}_{x}$ Switching Dielectrics
2011 · X. A. Tran, H. Y. Yu, et al. · IEEE Electron Device Letters · 21
Efficiency of mechanical stressors in Planar FDSOI n and p MOSFETs down to 14nm gate length
2012 · S. Morvan, F. Andrieu, et al. · Symposium on VLSI Technology · 20
Uniaxial-biaxial stress hybridization for super-critical strained-si directly on insulator (SC-SSOI) PMOS with different channel orientations.
2006 · A.V.-Y. Thean, L. Prabhu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 20
Performance of super-critical strained-si directly on insulator (SC-SSOI) CMOS based on high-performance PD-SOI technology
2005 · A.V.Y. Thean, T. White, et al. · Symposium on VLSI Technology · 17
Advanced FD-SOI and Beyond Low Temperature SmartCut™ Enables High Density 3-D SoC Applications
2019 · W. Schwarzenbach, N. Daval, et al. · IEEE Journal of the Electron Devices Society · 15
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AC transconductance: A novel method to characterize oxide traps in advanced FETs without a body contact
2012 · X. Sun, N. Xu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 15
On the origin of the mobility reduction in bulk-Si, UTBOX-FDSOI and SiGe devices with ultrathin-EOT dielectrics
2011 · L.-A. Ragnarsson, J. Mitard, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 15
Unified self-heating effect model for advanced digital and analog technology and thermal-aware lifetime prediction methodology
2017 · H. Jiang, L. Shen, et al. · Symposium on VLSI Technology · 13
Strain-Enhanced CMOS Through Novel Process-Substrate Stress Hybridization of Super-Critically Thick Strained Silicon Directly on Insulator (SC-SSOI)
2006 · C. Mazure, I. Cayrefourcq, et al. · Symposium on VLSI Technology · 13
CVD growth of Si Nanocrystals on Dielectric Surfaces for Nanocrystal Floating Gate Memory Application
2000 · Sucharita Madhukar, K. Smith, et al. · MRS Proceedings · 13
Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications
2019 · A. Vandooren, Z. Wu, et al. · Symposium on VLSI Technology · 10
Ultimate Layer Stacking Technology for High Density Sequential 3D Integration
2023 · I. Radu, B-Y. Nguyen, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 9
Works count: 45
Citation count: 737
H-index: 17
I10-index: 24
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