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Yusuke Kohyama

Observed names: Y. Kohyama, Y.Kohyama, Yusuke KOHYAMA
Institution: Toshiba (Japan)
OpenAlex ID: A5043584243
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
2005 · H.S. Yang, R. Malik, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 143
Suppression of crosstalk by using backside deep trench isolation for 1.12μm backside illuminated CMOS image sensor
2012 · Y. Kitamura, H. Aikawa, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 46
Future directions for DRAM memory cell technology
2002 · A. Nitayama, Y. Kohyama, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 31
Control of Two Types of Dielectric Relaxation Current for Ta2O5Metal-Insulator-Metal Capacitors
2003 · Masahiro Kiyotoshi, Katsuhiko Hieda, et al. · Japanese Journal of Applied Physics · 12
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High performance CMOS devices on SOI for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering
2003 · H. Park, W. Clark, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 7
Integration technology of polymetal (W/WSiN/Poly-Si) dual gate CMOS for 1 Gbit DRAMs and beyond
2002 · Y. Hiura, A. Azuma, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 6
Level-specific strategy of KrF microlithography for 130 nm DRAMs
2003 · S. Inoue, M. Asano, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 4
A 0.15 μm KrF lithography for 1 Gb DRAM product using highly printable patterns and thin resist process
2002 · T. Ozaki, T. Azuma, et al. · Symposium on VLSI Technology · 4
Boron diffusion layer formation using Ge cryogenic implantation with low-temperature microwave annealing
2016 · Atsushi Murakoshi, Tsubasa Harada, et al. · Japanese Journal of Applied Physics · 3
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A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs
1990 · T. Furuyama, H. Ishiuchi, et al. · IEEE Journal of Solid-State Circuits · 3
Coaxial‐line type microwave plasma CVD system to fabricate SiN films
1986 · Isamu Kato, Yusuke Kohyama, et al. · Electronics and Communications in Japan (Part II Electronics) · 3
Body voltage and history effect sensitivity to key device parameters in 90 nm PD-SOI
2004 · S. Kawanaka, H. Utomo, et al. · IEEE International SOI Conference (SOI) · 2
Liner-supported cylinder (LSC) technology to realize Ru/Ta/sub 2/O/sub 5//Ru capacitor for future DRAMs
2000 · Y. Fukuzumi, T. Suzuki, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 2
Low temperature (Ba,Sr)TiO/sub 3/ capacitor process integration (LTB) technology for gigabit scaled DRAMs
1999 · K. Hieda, K. Eguchi, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 2
Reduction in number of crystal defects in a p + Si diffusion layer by germanium and boron cryogenic implantation combined with sub-melt laser spike annealing
2017 · Atsushi Murakoshi, Tsubasa Harada, et al. · Japanese Journal of Applied Physics · 1
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A novel bit-line process using poly-Si masked dual-damascene (PMDD) for 0.13 μm DRAMs and beyond
2002 · T. Miyashita, H. Nitta, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 1
Chemical Vapor Deposition and Electrode Technologies for (Ba,Sr)TiO3 Capacitor Used in Gigabit Dram
1999 · K. Eguchi, K. Hieda, et al. · MRS Proceedings · 1
All perovskite capacitor (APEC) technology for (Ba,Sr)TiO/sub 3/ capacitor scaling toward 0.10 /spl mu/m stacked DRAMs
1998 · K. Hieda, K. Eguchi, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 1
Buried bit-line cell for 64 Mb DRAMs
1990 · Y. Kohyama, T. Yamamoto, et al. · Symposium on VLSI Technology · 1
Fabrication of a-Si: H thin films by a double tubed coaxial-line type microwave plasma CVD system.
1985 · Isamu KATO, Motoyasu YANO, et al. · Shinku · 1
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A 1.4μm pixel backside illumination CMOS image sensor with 300mm wafer based on 65 nm Logic Technology
2009 · Y. Kohyama
Control of 2 type Dielectric Relaxation Current of Ta2O5 Metal-Insulator-Metal[MIM]Capacitors
2002 · Masahiro Kiyotoshi, Katsuhiko Hieda, et al. · International Conference on Solid State Devices and Materials (SSDM)
Impact of Thermal Budget Reduction on MOSFET Performance to Achieve High-speed and High-density DRAM-based System LSI
2002 · E. Yoshida, T. Miyashita, et al. · International Conference on Solid State Devices and Materials (SSDM)
Reduction of Whisker-Originated Short between W Polymetal and Contact Plug
2001 · Yasushi Akasaka, Hiroshi Suzuki, et al. · MRS Proceedings
Backend process for cylindrical Ru/Ta/sub 2/O/sub 5//Ru capacitor for future DRAM
2001 · J. Lin, T. Suzuki, et al. · IEEE International Conference on Solid-State and Integrated Circuit Technology
Works count: 29
Citation count: 274
H-index: 6
I10-index: 4
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