Author

Patrick Jaenen

Observed name: P. Jaenen

Institution: IMEC

Observed institutions: Ghent University, IMEC, KU Leuven

OpenAlex ID: A5057759792

Compact Wavelength-Selective Functions in Silicon-on-Insulator Photonic Wires

2006 · Wim Bogaerts, Pieter Dumon, et al. · IEEE Journal of Selected Topics in Quantum Electronics · 337

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Fabrication of Photonic Wire and Crystal Circuits in Silicon-on-Insulator Using 193-nm Optical Lithography

2009 · S.K. Selvaraja, P. Jaenen, et al. · Journal of Lightwave Technology · 222

Compact wavelength router based on a Silicon-on-insulator arrayed waveguide grating pigtailed to a fiber array

2006 · P. Dumon, W. Bogaerts, et al. · Optics Express · 135

Pitch doubling through dual-patterning lithography challenges in integration and litho budgets

2007 · Mircea Dusa, John Quaedackers, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 92

Linear and Nonlinear Nanophotonic Devices Based on Silicon-on-Insulator Wire Waveguides

2006 · Pieter Dumon, Gino Priem, et al. · Japanese Journal of Applied Physics · 76

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Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

2011 · A. Redolfi, D. Velenis, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 52

3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias

2011 · Yann Civale, Deniz Sabuncuoglu Tezcan, et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 49

Evaluation of Megasonic Cleaning for Sub-90nm Technologies

2005 · Guy Vereecke, Frank Holsteyns, et al. · Diffusion and defect data, solid state data. Part B, Solid state phenomena/Solid state phenomena · 49

Study of novel EUVL mask absorber candidates

2021 · Meiyi Wu, Devesh Thakare, et al. · Journal of Micro/Nanopatterning Materials and Metrology · 30

Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping

2009 · Y. Civale, D. Sabuncuoglu Tezcan, et al. · IEEE International Conference on 3D System Integration (3DIC) · 27

A 0.314μm/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography

2005 · A. Nackaerts, M. Ercken, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 22

Silicon-on-insulator nanophotonics

2005 · Wim Bogaerts, Pieter Dumon, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 21

Split and design guidelines for double patterning

2008 · Vincent Wiaux, Staf Verhaegen, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 19

Basic photonic wire components in silicon-on-insulator

2005 · P. Dumon, G. Roelkens, et al. · IEEE International Conference on Group IV Photonics (GFP) · 17

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High Q inductor add-on module in thick Cu/SiLK/sup TM/ single damascene

2001 · S. Jenei, S. Decoutere, et al. · IEEE International Interconnect Technology Conference (IITC) · 17

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

2010 · A. Mercha, A. Redolfi, et al. · Symposium on VLSI Technology · 16

Silicon nanophotonic wire structures fabricated by 193nm optical lithography

2007 · Shankar Kumar Selvaraja, Patrick Jaenen, et al. · IEEE Lasers and Electro-Optics Society Annual Meeting (LEOS) · 13

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Implementation of high-k and metal gate materials for the 45nm node and beyond: gate patterning development

2005 · S. Beckx, M. Demand, et al. · Microelectronics Reliability · 13

Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274μm/sup 2/ 6t-sram cell and advanced CMOS logic circuits

2005 · L. Witters, N. Collaert, et al. · Symposium on VLSI Technology · 12

Reduction of mask-induced CD errors by optical proximity correction

1998 · John Randall, Alexander V. Tritchkov, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 12

Via-middle through-silicon via with integrated airgap to zero TSV-induced stress impact on device performance

2013 · Yann Civale, Stefaan Van Huylenbroeck, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 10

Reducing the impact of etch-induced pattern shift on overlay by using lithography and etch tool corrections

2017 · Michael Kubis, Rich Wise, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 9

NA/σ optimization strategies for an advanced DUV stepper applied to 0.25-μm and sub-0.25-μm critical levels

1997 · Maaike Op de Beeck, Kurt G. Ronse, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 9

Improving the performance and usability of a wet-developable DUV resist for sub-500nm lithography

1991 · Nandasiri Samarakone, Veerle Van Driessche, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 6

Mask absorber for next generation EUV lithography

2020 · Meiyi Wu, Devesh Thakare, et al. · 5

Works count: 61

Citation count: 1,331

H-index: 16

I10-index: 21