A 0.314μm/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography
Year: 2005
Type: conference-paper
Authors: A. Nackaerts, M. Ercken, S. Demuynck, A. Lauwers, C. Baerts, H. Bender, W. Boulaert, N. Collaert, B. Degroote, C. Delvaux, J.F. de Marneffe, A. Dixit, K. De Meyera, E. Mendrickx, N. Heylen, P. Jaenen, D. Laidler, S. Locorotondo, M. Maenhoudt, M. Moclants, I. Pollentier, K. Ronse, R. Rooyackers, J. Van Aelst, G. Vandenberghe, W. Vandervorst, T. Vandeweyer, S. Vanhaelemeersch, M. Van Hove, J. Van Olmen, S. Verhaegen, J. Versluijs, C. Vrancken, V. Wiaux, M. Jurczak, S. Biesemans
Institutions: IMEC, KU Leuven, Philips (Belgium)
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: closed
OpenAlex ID: W1600912424