Author

Staf Verhaegen

Observed names: S. Verhaegen, Sta Verhaegen

Institution: IMEC

Observed institution: IMEC

OpenAlex ID: A5111929035

Double patterning design split implementation and validation for the 32nm node

2007 · Martin Drapeau, Vincent Wiaux, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 96

Double pattern EDA solutions for 32nm HP and beyond

2007 · George E. Bailey, Alexander Tritchkov, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 78

Interactions of double patterning technology with wafer processing, OPC and design flows

2008 · Kevin Lucas, Chris Cork, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 23

Freeform illumination sources: an experimental study of source-mask optimization for 22-nm SRAM cells

2010 · J. Bekaert, B. Laenens, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 22

A 0.314μm/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography

2005 · A. Nackaerts, M. Ercken, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 22

Split and design guidelines for double patterning

2008 · Vincent Wiaux, Staf Verhaegen, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 19

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

2009 · A. Veloso, S. Demuynck, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 15

Double-patterning interactions with wafer processing, optical proximity correction, and physical design flows

2009 · Kevin Lucas, Christopher M. Cork, et al. · Journal of Micro/Nanopatterning Materials and Metrology · 15

Patterning challenges in setting up a 16nm node 6T-SRAM device using EUV lithography

2011 · Tom Vandeweyer, Johan De Backer, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 12

Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274μm/sup 2/ 6t-sram cell and advanced CMOS logic circuits

2005 · L. Witters, N. Collaert, et al. · Symposium on VLSI Technology · 12

Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell

2008 · A. Veloso, S. Demuynck, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 9

High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

2010 · N. Horiguchi, S. Demuynck, et al. · Symposium on VLSI Technology · 8

Assessment of OPC effectiveness using two-dimensional metrics

2002 · Vincent Wiaux, Vicky Philipsen, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 7

Litho variations and their impact on the electrical yield of a 32nm node 6T SRAM cell

2008 · Staf Verhaegen, Stefan Cosemans, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 5

Challenges in patterning 45nm node multiple-gate devices and SRAM cells

2004 · Monique Ercken, Christie Delvaux, et al. · 5

Limits of optical lithography

2000 · Mireille Maenhoudt, Staf Verhaegen, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 5

Litho-process-litho for 2D 32nm hp Logic and DRAM double patterning

2010 · Patrick Wong, Vincent Wiaux, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 4

Challenges in using optical lithography for the building of a 22nm node 6T-SRAM cell

2009 · M. Ercken, E. Altamirano-Sanchez, et al. · Microelectronic Engineering · 4

A methodology for double patterning compliant split and design

2008 · Vincent Wiaux, Staf Verhaegen, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 4

Printability verification for double-patterning technology

2008 · Gerard Luk-Pat, Petrisor Panaite, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 4

Checking design conformance and optimizing manufacturability using automated double patterning decomposition

2008 · Chris Cork, Brian Ward, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 4

Optical extensions integration for a 0.314-μm245-nm node 6-transistor SRAM cell

2005 · Staf Verhaegen, Axel Nackaerts, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 4

Integration of tall triple-gate devices with inserted TaxNy gate in a 0.274µm2 6T-SRAM cell and advanced CMOS logic circuits

2005 · Liesbeth Witters, N. Collaert, et al. · 4

Model-based OPC for first-generation 193-nm lithography

2001 · Kevin D. Lucas, James C. Word, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 4

Immersion lithography and double patterning in advanced microelectronics

2009 · T. Vandeweyer, J. Bekaert, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 3

Works count: 41

Citation count: 412

H-index: 10

I10-index: 10