Author

Tom Vandeweyer

Observed names: T. Vandeweye, T. Vandeweyer, Vandeweyer Tom

Institution: IMEC

Observed institutions: IMEC, Philips (Belgium), KU Leuven

OpenAlex ID: A5086967487

10×10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation

2011 · B. Govoreanu, G.S. Kar, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 649

Highly reliable TaOx ReRAM with centralized filament for 28-nm embedded application

2015 · Y. Hayakawa, A. Himeno, et al. · Symposium on VLSI Technology · 94

Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography

2007 · M.J.H. van Dal, N. Collaert, et al. · Symposium on VLSI Technology · 81

A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM

2007 · K. von Arnim, E. Augendre, et al. · Symposium on VLSI Technology · 79

A new complementary hetero-junction vertical Tunnel-FET integration scheme

2013 · R. Rooyackers, A. Vandooren, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 62

Record ION/IOFF performance for 65nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability

2008 · J. Mitard, B. De Jaeger, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 57

High Performance 70-nm Germanium pMOSFETs With Boron LDD Implants

2008 · G. Hellings, G. Hellings, et al. · IEEE Electron Device Letters · 51

Ge-Source Vertical Tunnel FETs Using a Novel Replacement-Source Integration Scheme

2014 · Rita Rooyackers, Anne Vandooren, et al. · IEEE Transactions on Electron Devices · 48

Double patterning lithography for 32 nm: critical dimensions uniformity and overlay control considerations

2009 · Jo M. Finders, Mircea V. Dusa, et al. · Journal of Micro/Nanopatterning Materials and Metrology · 44

Double patterning for 32nm and below: an update

2008 · Jo Finders, Mircea Dusa, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 42

Low temperature plasma-enhanced ALD enables cost-effective spacer defined double patterning (SDDP)

2009 · Julien Beynet, Patrick Wong, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 36

Advanced Cu interconnects using air gaps

2005 · L.G. Gosset, A. Farcy, et al. · Microelectronic Engineering · 36

Gatestacks for scalable high-performance FinFETs

2007 · G. Vellianitis, J. Petry, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 34

Spacer defined FinFET: Active area patterning of sub-20nm fins with high density

2006 · B. Degroote, R. Rooyackers, et al. · Microelectronic Engineering · 32

Highly reliable TaOx ReRAM with centralized filament for 28-nm embedded application

2015 · Y. Hayakawa, A. Himeno, et al. · Symposium on VLSI Circuits · 30

Calibration and verification of a stochastic model for EUV resist

2012 · Weimin Gao, Alexander Philippou, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 29

Record low contact resistivity to n-type Ge for CMOS and memory applications

2010 · K. Martens, A. Firrincieli, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 24

A Novel Fully Self-Aligned SiGe:C HBT Architecture Featuring a Single-Step Epitaxial Collector-Base Process

2007 · J.J.T.M. Donkers, T. Vanhoucke, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 23

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

2006 · R. Rooyackers, E. Augendre, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 23

A 400GHz fMAX fully self-aligned SiGe:C HBT architecture

2009 · S. Van Huylenbroeck, A. Sibaja-Hernandez, et al. · IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) · 22

A 0.314μm/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography

2005 · A. Nackaerts, M. Ercken, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 22

Litho and patterning challenges for memory and logic applications at the 22-nm node

2010 · Jo Finders, Mircea Dusa, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 21

Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

2008 · N. Collaert, K. von Arnim, et al. · IEEE International Conference on IC Design and Technology (ICICDT) · 19

Bulk FinFET fabrication with new approaches for oxide topography control using dry removal techniques

2011 · A. Redolfi, S. Kubicek, et al. · Solid-State Electronics · 16

In-Line Metrology for Characterization and Control of Extreme Wafer Thinning of Bonded Wafers

2018 · M. Liebens, A. Jourdain, et al. · IEEE Transactions on Semiconductor Manufacturing · 15

Works count: 62

Citation count: 1,755

H-index: 21

I10-index: 30