Author

Mireille Maenhoudt

Observed names: M Maenhoudt, M. Maenhoudt

Institution: IMEC

Observed institution: IMEC

OpenAlex ID: A5041975413

Pitch doubling through dual-patterning lithography challenges in integration and litho budgets

2007 · Mircea Dusa, John Quaedackers, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 92

Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm

2005 · M. Maenhoudt, J. Versluijs, et al. · Optical Microlithography XVIII · 52

Double patterning lithography for 32 nm: critical dimensions uniformity and overlay control considerations

2009 · Jo M. Finders, Mircea V. Dusa, et al. · Journal of Micro/Nanopatterning Materials and Metrology · 44

Double patterning for 32nm and below: an update

2008 · Jo Finders, Mircea Dusa, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 42

Low temperature plasma-enhanced ALD enables cost-effective spacer defined double patterning (SDDP)

2009 · Julien Beynet, Patrick Wong, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 36

Novel aberration monitor for optical lithography

1999 · Peter Dirksen, Casper A. H. Juffermans, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 31

Alternative process schemes for double patterning that eliminate the intermediate etch step

2008 · M. Maenhoudt, R. Gronheid, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 29

Lithography Options for the 32 nm Half Pitch Node and Beyond

2009 · K. Ronse, P. Jansen, et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 26

Printing the metal and contact layers for the 32- and 22-nm node: comparing positive and negative tone development process

2010 · L. Van Look, J. Bekaert, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 25

A 0.314μm/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography

2005 · A. Nackaerts, M. Ercken, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 22

Characterisation and integration feasibility of JSR’s low-k dielectric LKD-5109

2002 · A Das, T Kokubo, et al. · Microelectronic Engineering · 22

Split and design guidelines for double patterning

2008 · Vincent Wiaux, Staf Verhaegen, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 19

Double Patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm

2005 · Mireille Maenhoudt · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 19

Integration of Cu and low-k dielectrics: effect of hard mask and dry etch on electrical performance of damascene structures

2001 · R.A. Donaton, B. Coenegrachts, et al. · Microelectronic Engineering · 18

Immersion specific defect mechanisms: findings and recommendations for their control

2006 · Michael Kocsis, Dieter Van Den Heuvel, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 17

Process Optimization and Integration of Trimethylsilane-Deposited α-SiC:H and α-SiCO:H Dielectric Thin Films for Damascene Processing

2003 · W. D. Gray, M. J. Loboda, et al. · Journal of The Electrochemical Society · 13

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Recent Progress in ArF Lithography for the 100nm Node.

2001 · A.M. Goethals, G. Vandenberghe, et al. · Journal of Photopolymer Science and Technology · 13

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Ultimate contact hole resolution using immersion lithography with line/space imaging

2009 · V. Truffert, J. Bekaert, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 12

Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274μm/sup 2/ 6t-sram cell and advanced CMOS logic circuits

2005 · L. Witters, N. Collaert, et al. · Symposium on VLSI Technology · 12

Lithography options for the 32nm half pitch node and their implications on resist and material technology

2007 · Roel Gronheid, Eric Hendrickx, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 11

Integration of 20nm half pitch single damascene copper trenches by spacer-defined double patterning (SDDP) on metal hard mask (MHM)

2010 · Yong Kong Siew, Janko Versluijs, et al. · IEEE International Interconnect Technology Conference (IITC) · 10

Top coat or no top coat for immersion lithography?

2006 · N. Stepanenko, Hyun-Woo Kim, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 10

NA/σ optimization strategies for an advanced DUV stepper applied to 0.25-μm and sub-0.25-μm critical levels

1997 · Maaike Op de Beeck, Kurt G. Ronse, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 9

Impact of water and top-coats on lithographic performance in 193-nm immersion lithography

2005 · Shinji Kishimura, Roel Gronheid, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 8

Dense lines created by spacer DPT scheme: process control by local dose adjustment using advanced scanner control

2009 · Jo Finders, Mircea Dusa, et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 7

Works count: 61

Citation count: 695

H-index: 15

I10-index: 22