Author

A. Pangal

Observed institution: Intel (United States)

OpenAlex ID: A5063443271

1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS

2003 · S. Narendra, M. Haycock, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 65

5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS

2002 · S. Vangal, M.A. Anders, et al. · IEEE Journal of Solid-State Circuits · 35

A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes

2002 · R. Nair, N.Y. Borkar, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 18

1.1V 1GHz communications router with on-chip body bias in 150nm CMOS

2005 · S. Narendra, M. Haycock, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 9

A 25 GHz 32 b integer-execution core in 130 nm dual-V/sub T/ CMOS

2003 · S. Vangal, N. Borkar, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 8

5GHz 32b integer-execution core in 130nm dual-V/sub T/ CMOS

2005 · S. Vangal, N. Borkar, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 2

Works count: 6

Citation count: 137

H-index: 5

I10-index: 3