Get started
Author

Rezaul Haque

30.2 A 1Tb 4b/Cell 144-Tier Floating-Gate 3D-NAND Flash Memory with 40MB/s Program Throughput and 13.8Gb/mm2 Bit Density
2021 · Ali Khakifirooz, Sriram Balasubrahmanyam, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 47
A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-nand Technology and Featuring a 23.3 Gb/mm 2 Bit Density
2023 · Ali Khakifirooz, Eduardo Anaya, et al. · IEEE Solid-State Circuits Letters · 24
A 90nm 512mb 166MHz multilevel cell flash memory with 1.5MByte/s programming
2005 · M. Taub, R. Bains, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 19
A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-NAND Technology and Featuring a 23.3Gb/mm2 Bit Density
2023 · Ali Khakifirooz, Eduardo Anaya, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 15
Extraction of motion parameters of gravity-wave structures from all-sky OH image sequences
1999 · Rezaul Haque, Gary R. Swenson · Applied Optics · 14
A 321-Layer 2Tb 4b/cell 3D-NAND-Flash Memory with a 75MB/s Program Throughput
2025 · Wanik Cho, Chanhui Jeong, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 10
A 1.8 V 64 Mb 100 MHz flexible read while write flash memory [in CMOS]
2002 · B. Pathak, A. Cabrera, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 9
A 125MHz burst mode 0.18μm 128Mbit 2 bits per cell flash memory
2003 · H.A. Castro, K. Augustine, et al. · Symposium on VLSI Circuits · 7
On-chip charge pump design for 3D non-volatile flash memory: from industry perspective
2023 · Rezaul Haque, Siraj Fulum Mossa · Integration · 3
Application of Negative Pump for Higher bits/cell in Circuit-Under Array 3D NAND Flash Memory
2023 · Siraj Mossa, Rezaul Haque · 2
Design of a flash-based reference voltage generator for drain bias circuit
2007 · R. Haque, K. Tedrow, et al. · IET Circuits Devices & Systems
Design of a high-speed, low-noise CMOS data output buffer
2005 · Rezaul Haque, Andrzej Sendrowski, et al. · Integration
Works count: 12
Citation count: 150
H-index: 7
I10-index: 6
Year
Topic
Type