Author

Young-Il Lim

Observed names: Y.D. Lim, Youngil Lim

Institutions: Samsung (South Korea), Samsung Electronics (South Korea)

Observed institutions: Samsung (South Korea), Institute of Electrical and Electronics Engineers, Samsung Electronics (South Korea)

ORCID: 0000-0002-5773-0296

Observed ORCID: 0000-0002-5773-0296

OpenAlex ID: A5069859342

Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications

2011 · H.-J. Cho, K.-I. Seo, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 28

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

2020 · Hyung-Joon Chi, Chang-Kyo Lee, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 27

Implementation of HIGHT cryptic circuit for RFID tag

2009 · Young-Il Lim, Je-Hoon Lee, et al. · IEICE Electronics Express · 22

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An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques

2020 · Chang-Kyo Lee, Hyung-Joon Chi, et al. · IEEE Journal of Solid-State Circuits · 19

Highly Manufacturable Low Power and High Performance 11LPP Platform Technology for Mobile and GPU Applications

2018 · H.-J. Kim, B.H. Choi, et al. · Symposium on VLSI Technology · 6

Implementation of IEEE 802.11a WLAN Baseband Processor

2007 · Je-Hoon Lee, Young-Il Lim, et al. · International Conference on Consumer Electronics

Design of Asynchronous System Bus Wrappers based on a Hybrid Ternary Data Encoding Scheme

2007 · Young-Il Lim, Je-Hoon Lee, et al. · Journal of the Institute of Electronics Engineers of Korea

Asynchronous Wrapper Design based on Hybrid Ternary Data Encoding Scheme

2006 · Young-Il Lim, Je-Hoon Lee, et al. · 대한전자공학회 ISOCC

Works count: 8

Citation count: 102

H-index: 5

I10-index: 4