Author

S. Deleonibus

Observed names: DELEONIBUS S., Deleonibus, Deleonibus, S., Deleonibus, Simon, S Deleonibus, S. DELEONIBUS, S. Deleonibus., S. Deléonibus, S.Deleonibus, Simon DELEONIBUS, Simon Deleonibus

Observed institutions: Soitec (France), Tokyo Institute of Technology, Centre National de la Recherche Scientifique, Université Côte d'Azur, Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Micro and Nanotechnology Innovation Centre, Laboratoire d’Innovation pour les Technologies des Énergies Nouvelles et les nanomatériaux, CEA Grenoble, Japan Science and Technology Agency, Qualcomm (United States), STMicroelectronics (France), Direction de la Recherche Technologique, Institut de Microélectronique, Electromagnétisme et Photonique, Laboratoire d'Électronique des Technologies de l'Information, Atmel (France), Université Grenoble Alpes

ORCID: 0000-0002-3399-5097

Observed ORCID: 0000-0002-3399-5097

OpenAlex ID: A5076856577

Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET performance

2008 · F. Mayer, C. Le Royer, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 251

High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding

2008 · O. Weber, O. Faynot, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 194

Advances, challenges and opportunities in 3D CMOS sequential integration

2011 · P. Batude, M. Vinet, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 164

FDSOI devices with thin BOX and ground plane integration for 32nm node and below

2009 · C. Fenouillet-Beranger, S. Denorme, et al. · Solid-State Electronics · 147

Lateral interband tunneling transistor in silicon-on-insulator

2004 · C. Aydin, A. Zaslavsky, et al. · Applied Physics Letters · 146

Multiple gate devices: advantages and challenges

2005 · T. Poiroux, M. Vinet, et al. · Microelectronic Engineering · 140

Bonded planar double-metal-gate NMOS transistors down to 10 nm

2005 · M. Vinet, T. Poiroux, et al. · IEEE Electron Device Letters · 138

Advances in 3D CMOS sequential integration

2009 · P. Batude, M. Vinet, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 130

15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET

2008 · C. Dupre, A. Hubert, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 126

Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond

2010 · O. Faynot, F. Andrieu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 114

Simple and controlled single electron transistor based on doping modulation in silicon nanowires

2006 · M. Hofheinz, X. Jehl, et al. · Applied Physics Letters · 104

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Performance and Reliability Features of Advanced Nonvolatile Memories Based on Discrete Traps (Silicon Nanocrystals, SONOS)

2004 · B. DeSalvo, C. Gerardi, et al. · IEEE Transactions on Device and Materials Reliability · 92

Size Dependence of Surface-Roughness-Limited Mobility in Silicon-Nanowire FETs

2008 · Stefano Poli, Marco G. Pala, et al. · IEEE Transactions on Electron Devices · 87

Experimental Evaluation of Gate Architecture Influence on DG SOI MOSFETs Performance

2005 · J. Widiez, J. Lolivier, et al. · IEEE Transactions on Electron Devices · 87

How far will silicon nanocrystals push the scaling limits of NVMs technologies?

2004 · B. De Salvo, C. Gerardi, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 80

Individual charge traps in silicon nanowires: Measurements of location, spin and occupation number by Coulomb blockade spectroscopy

2006 · M. Hofheinz, X. Jehl, et al. · The European Physical Journal B · 77

3D monolithic integration: Technological challenges and electrical results

2010 · M. Vinet, P. Batude, et al. · Microelectronic Engineering · 76

Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm 2 6T-SRAM bitcell

2007 · C. Fenouillet-Beranger, J. Todeschini, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 74

75 nm damascene metal gate and high-k integration for advanced CMOS devices

2003 · B. Guillaumot, X. Garros, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 72

Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack

2006 · T. Ernst, C. Dupre, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 71

Novel Si-based nanowire devices: Will they serve ultimate MOSFETs scaling or ultimate hybrid integration?

2008 · T. Ernst, L. Duraffourg, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 61

Individual charge traps in silicon nanowires: Measurements of location, spin and occupation number by Coulomb blockade spectroscopy

2005 · Hofheinz, M., Jehl, X., et al. · arXiv (Cornell University) · 61

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Strained FDSOI CMOS technology scalability down to 2.5nm film thickness and 18nm gate length with a TiN/HfO2 gate stack

2007 · V. Barral, T. Poiroux, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 57

Reduction of fixed charges in atomic layer deposited Al2O3 dielectrics

2005 · J. Buckley, B. De Salvo, et al. · Microelectronic Engineering · 57

Static and Dynamic TCAD Analysis of IMOS Performance: From the Single Device to the Circuit

2006 · F. Mayer, C. Le Royer, et al. · IEEE Transactions on Electron Devices · 54

Works count: 385

Citation count: 5,722

H-index: 38

I10-index: 127