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Andres Bryant
Observed name:
A. Bryant
Institution:
IBM Research - Albany
Observed institutions:
IBM (United States),
GlobalFoundries (United States),
IBM Research - Thomas J. Watson Research Center,
IBM Research - Albany
OpenAlex ID:
A5084787422
Silicon CMOS devices beyond scaling
2006
·
W. Haensch
, E. J. Nowak
, et al.
·
IBM Journal of Research and Development
·
471
Ultralow-voltage, minimum-energy CMOS
2006
·
S. Hanson
, B. Zhai
, et al.
·
IBM Journal of Research and Development
·
215
High performance 14nm SOI FinFET CMOS technology with 0.0174µm 2 embedded DRAM and 15 levels of Cu metallization
2014
·
C-H. Lin
, B. Greene
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
133
FinFET performance advantage at 22nm: An AC perspective
2008
·
M. Guillorn
, J. Chang
, et al.
·
Symposium on VLSI Technology
·
86
Low-power CMOS at Vdd=4kT/q
2002
·
A. Bryant
, J. Brown
, et al.
·
Conference digest
·
80
Channel doping impact on FinFETs for 22nm and beyond
2012
·
C.-H. Lin
, R. Kambhampati
, et al.
·
Symposium on VLSI Technology
·
69
GIDL in Doped and Undoped FinFET Devices for Low-Leakage Applications
2012
·
Pranita Kerber
, Qintao Zhang
, et al.
·
IEEE Electron Device Letters
·
65
A 7nm CMOS technology platform for mobile and high performance compute application
2017
·
S. Narasimha
, B. Jagannathan
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
62
Characteristics of CMOS device isolation for the ULSI age
2002
·
A. Bryant
, W. Hansch
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
57
Energy optimality and variability in subthreshold design
2006
·
Scott Hanson
, Bo Zhai
, et al.
·
International Symposium on Low Power Electronics and Design (ISLPED)
·
46
Mainstreaming of the SOI technology
1999
·
G. Shahidi
, H.-S. Lo
, et al.
·
IEEE International SOI Conference (SOI)
·
39
The effects of gate field on the leakage characteristics of heavily doped junctions
1989
·
W.P. Noble
, S.H. Voldman
, et al.
·
IEEE Transactions on Electron Devices
·
38
The current-carrying corner inherent to trench isolation
1993
·
A. Bryant
, W. Haensch
, et al.
·
IEEE Electron Device Letters
·
35
Sub-25nm FinFET with advanced fin formation and short channel effect engineering
2011
·
Takashi Yamashita
, V. Basker
, et al.
·
Symposium on VLSI Technology
·
34
Comprehensive study of effective current variability and MOSFET parameter correlations in 14nm multi-fin SOI FINFETs
2013
·
A. Paul
, A. Bryant
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
33
Investigation of CMOS devices with embedded sige source/drain on hybrid orientation substrates
2005
·
Qiqing Ouyang
, Min Yang
, et al.
·
Symposium on VLSI Technology
·
25
Dual stress liner enhancement in hybrid orientation technology
2005
·
C.D. Sheraw
, M. Yang
, et al.
·
Symposium on VLSI Technology
·
25
Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond
2011
·
Chung-Hsun Lin
, Wilfried Haensch
, et al.
·
Symposium on VLSI Technology
·
24
A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs
2015
·
T. Yamashita
, S. Mehta
, et al.
·
Symposium on VLSI Technology
·
23
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm 2 SRAM cell
2011
·
Kangguo Cheng
, A. Khakifirooz
, et al.
·
Symposium on VLSI Circuits
·
19
Non-planar device architecture for 15nm node: FinFET or trigate?
2010
·
Chung-Hsun Lin
, Josephine Chang
, et al.
·
IEEE International SOI Conference (SOI)
·
18
Performance comparison and channel length scaling of strained Si FETs on SiGe-on-Insulator (SGOI)
2005
·
J. Cai
, K. Rim
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
18
Impact of Lateral Asymmetric Channel Doping on 45-nm-Technology N-Type SOI MOSFETs
2009
·
Hasan M. Nayfeh
, Nivo Rovedo
, et al.
·
IEEE Transactions on Electron Devices
·
15
Energy Optimality and Variability in Subthreshold Design
2006
·
Scott Hanson
, Bo Zhai
, et al.
·
International Symposium on Low Power Electronics and Design (ISLPED)
·
15
A fundamental performance limit of optimized 3.3-V sub-quarter-micrometer fully overlapped LDD MOSFET's
1992
·
A. Bryant
, B. El-Kareh
, et al.
·
IEEE Transactions on Electron Devices
·
15
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Works count:
44
Citation count:
1,748
H-index:
19
I10-index:
28
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