Get started
Author

Thomas J. Bucelot

Observed names: T. BUCELOT, T. Bucelot, T. J. Bucelot, T.J. Bucelot, Thomas Bucelot
OpenAlex ID: A5086941799
Indium channel implant for improved short-channel behavior of submicrometer NMOSFETs
1993 · G.G. Shahidi, B. Davari, et al. · IEEE Electron Device Letters · 72
Degradation of bipolar transistors under high current stress at 300 K
1988 · R. A. Wachnik, T. J. Bucelot, et al. · Journal of Applied Physics · 63
A Resonant Global Clock Distribution for the Cell Broadband Engine Processor
2009 · Steven C. Chan, Phillip J. Restle, et al. · IEEE Journal of Solid-State Circuits · 51
Loop-based interconnect modeling and optimization approach for multigigahertz clock network design
2003 · Xuejue Huang, P. Restle, et al. · IEEE Journal of Solid-State Circuits · 37
Resonant tunneling of holes through silicon barriers
1990 · Ulf Gennser, V. P. Kesan, et al. · Journal of Vacuum Science & Technology B Microelectronics Processing and Phenomena · 33
CPAM: a common power analysis methodology for high-performance VLSI design
2002 · J.S. Neely, H.H. Chen, et al. · IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS) · 26
Fabrication of high performance 512K static-random access memories in 0.25 μm complementary metal–oxide semiconductor technology using x-ray lithography
1993 · R. Viswanathan, D. Seeger, et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 24
A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor
2008 · Steven Chan, Phillip Restle, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 23
A highly latchup-immune 1-µm CMOS technology fabricated with 1-MeV ion implantation and self-aligned TiSi2
1986 · Fang-Shi J. Lai, L.K. Wang, et al. · IEEE Transactions on Electron Devices · 21
5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8TM microprocessor
2014 · Phillip Restle, David Shan, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 20
Temperature dependent transport measurements on strained Si/Si1−xGex resonant tunneling devices
1991 · Ulf Gennser, V. P. Kesan, et al. · Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena · 19
A 12-ns low-temperature DRAM
1989 · W.H. Henkels, N.C.C. Lu, et al. · IEEE Transactions on Electron Devices · 19
A 4-Mb low-temperature DRAM
1991 · W.H. Henkels, D.-S. Wen, et al. · IEEE Journal of Solid-State Circuits · 18
Photomagnetism of the triplet state of coronene
1980 · Charles J. O'Connor, Ekkehard Sinn, et al. · Chemical Physics Letters · 15
Enhanced performance of accumulation mode 0.5 mu m CMOS/SOI operated at 300 K and 85 K
2002 · L.K. Wang, J. Seliskar, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 13
SQUIDs for measuring the magnetic properties of materials
1978 · B. S. Deaver, Thomas J. Bucelot, et al. · AIP conference proceedings · 9
Low temperature SER and noise in a high speed DRAM
2003 · W.H. Henkels, N.C.C. Lu, et al. · Workshop on Low Temperature Semiconductor Electronics · 7
A low temperature 12 ns DRAM
2003 · W.H. Henkels, N.C.C. Lu, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 6
Fabrication of high performance 512Kb SRAMs in 0.25 μm CMOS technology using x-ray lithography
1994 · R. Viswanathan, D. Seeger, et al. · Microelectronic Engineering · 6
Superconducting lead particles produced by chemical techniques
1982 · T. L. Fariss, W. E. Nixon, et al. · Journal of Applied Physics · 6
Loop-based interconnect modeling and optimization approach for multi-GHz clock network design
2003 · Xuejue Huang, P. Restle, et al. · Custom Integrated Circuits Conference · 5
Resonant clock mega-mesh for the IBM z13TM
2015 · David Shan, Phillip Restle, et al. · Symposium on VLSI Circuits · 4
Infrastructure requirements for a large-scale, multi-site VLSI development project
2002 · G. P. Rodgers, I. G. Bendrihem, et al. · IBM Journal of Research and Development · 3
Process Integration for a 2ns Cycle/4ns Access 512K CMOS SRAM
1991 · R. Joshi, S. Klepner, et al. · Symposium on VLSI Technology · 3
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution
2005 · G. G. Lopez, G. Fiorenza, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 2
Works count: 34
Citation count: 515
H-index: 14
I10-index: 15
Year
Topic
Type