Work

Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution

Year: 2005

Type: conference-paper

Source: ACM Great Lakes Symposium on VLSI (GLSVLSI)

DOI: 10.1145/1057661.1057672

Authors: G. G. Lopez, G. Fiorenza, T. Bucelot, P. Restle, M. Y. Lanzerotti

Institutions: Georgia Institute of Technology, IBM Research - Thomas J. Watson Research Center

Language: English

Topic: VLSI and FPGA Design Techniques

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

SDG: Industry, innovation and infrastructure

Open Access status: closed

OpenAlex ID: W2163301607

FWCI:

Cites: 5

Cited by: 2

Related to: 10