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Kai Xue

Effect of thermal annealing on TSV Cu protrusion and local stress
2014 · Xiangmeng Jing, Hongwen He, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 24
Properties and electric characterizations of tetraethyl orthosilicate-based plasma enhanced chemical vapor deposition oxide film deposited at 400°C for through silicon via application
2013 · Meiying Su, Daquan Yu, et al. · Thin Solid Films · 19
High frequency characterization and analysis of through silicon vias and coplanar waveguides for silicon interposer
2014 · Huijuan Wang, Xiaoli Ren, et al. · Microsystem Technologies · 9
Effect of annealing after copper plating on the pumping behavior of through silicon vias
2014 · Liang Ji, Xiangmeng Jing, et al. · International Conference on Electronic Packaging Technology (ICEPT) · 9
Design, analysis and test of high-frequency interconnections in 2.5D package with silicon interposer
2016 · Xiaoli Ren, Cheng Pang, et al. · Journal of Semiconductors · 7
The study of backside TSV reveal process by direct Si/Cu grinding and polishing
2013 · Kai Xue, Daquan Yu, et al. · IEEE Electronics Packaging Technology Conference (EPTC) · 5
Design, simulation, and process development for 2.5D TSV interposer for high performance processer packaging
2013 · Xiaoli Ren, Kai Xue, et al. · IEEE CPMT Symposium Japan (ICSJ) · 5
Integrated process for high aspect ratio through glass vias
2017 · Xue Kai, Jiang Feng, et al. · International Conference on Electronic Packaging Technology (ICEPT) · 4
Influence of thermal annealing on the deformation of Cu-filled TSV
2014 · Hongwen He, Xiangmeng Jing, et al. · Electronic System-Integration Technology Conference (ESTC) · 2
Wafer level warpage characterization for backside manufacturing processes of TSV interposers
2014 · Feng Jiang, Qibin Wang, et al. · IEEE Electronic Components and Technology Conference (ECTC) · 2
Investigation of temporary bonding and release processes for TSV with copper pillar bumps
2014 · Xiangmeng Jing, Feng Jiang, et al. · International Conference on Electronic Packaging Technology (ICEPT) · 2
Fabrication of high Q factor integrated passive devices based on embedded Fan-out wafer level package
2017 · Xiufeng Zhou, Xuefei Ming, et al. · International Conference on Electronic Packaging Technology (ICEPT) · 1
Assembly process development of 2.5D integration for high performance processer
2015 · Haiyan Liu, Feng Jiang, et al. · International Conference on Electronic Packaging Technology (ICEPT) · 1
Key process development on 300mm wafer for 2.5D/3D integration
2015 · Chongshen Song, Kai Xue, et al. · IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) · 1
Signal integrity analysis of a high-performance processor package with silicon interposer
2014 · Xiaoli Ren, Cheng Pang, et al. · International Conference on Electronic Packaging Technology (ICEPT)
Works count: 15
Citation count: 91
H-index: 5
I10-index: 2
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