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René Schüffny

Observed names: R Schuffny, R. Schuffny, R. Schüffny, R. Schüffny, Rene Schueffny, Rene Schuffny, Rene Schüffny, Rene Schüffny, René Schüffny, René Schuffny, S. Schuffny, Schuffny, R., Schuffny, Rene, Schüffny, R., Schüffny, Rene, Schüffny, René
OpenAlex ID: A5110046407
Neuromorphic hardware in the loop: Training a deep spiking network on the BrainScaleS wafer-scale system
2017 · Sebastian Schmitt, Johann Klahn, et al. · International Joint Conference on Neural Networks (IJCNN) · 154
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Exploiting Memristive BiFeO3 Bilayer Structures for Compact Sequential Logics
2014 · Tiangui You, Yao Shuai, et al. · Advanced Functional Materials · 145
Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System
2017 · Schmitt, Sebastian, Klahn, Johann, et al. · TUGraz OPEN Library (Graz University of Technology) · 134
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A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits
2015 · Christian Mayr, Johannes Partzsch, et al. · IEEE Transactions on Biomedical Circuits and Systems · 112
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A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems
2011 · Daniel Brüderle, Mihai A. Petrovici, et al. · Biological Cybernetics · 100
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Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system
2012 · Johannes Schemmel, Andreas Grubl, et al. · IEEE International Symposium on Circuits and Systems proceedings · 65
Characterization and Compensation of Network-Level Anomalies in Mixed-Signal Neuromorphic Modeling Platforms
2014 · Mihai A. Petrovici, Bernhard Vogginger, et al. · PLoS ONE · 60
Practical guide for validated memristance measurements
2013 · Nan Du, Yao Shuai, et al. · Review of Scientific Instruments · 56
A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology
2013 · Sebastian Hoppner, Stefan Haenzsche, et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 51
Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS
2015 · Marko Noack, Johannes Partzsch, et al. · Frontiers in Neuroscience · 43
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A 32 GBit/s communication SoC for a waferscale neuromorphic system
2011 · Stefan Scholze, Holger Eisenreich, et al. · Integration · 43
Autonomous Chemical Oscillator Circuit Based on Bidirectional Chemical‐Microfluidic Coupling
2016 · Georgi Paschew, Jörg Schreiter, et al. · Advanced Materials Technologies · 40
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A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS
2012 · Dennis Walter, Sebastian Hoppner, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 40
Analyzing the Scaling of Connectivity in Neuromorphic Hardware and in Models of Neural Networks
2011 · J Partzsch, R Schuffny · IEEE Transactions on Neural Networks · 39
Modelling of capacitor mismatch and non-linearity effects ini charge redistribution SAR ADCs
2010 · Stefan Haenzsche, Stephan Henker, et al. · International Conference Mixed Design of Integrated Circuits and Systems · 39
A fixed point exponential function accelerator for a neuromorphic many-core system
2017 · Johannes Partzsch, Sebastian Hoppner, et al. · IEEE International Symposium on Circuits and Systems proceedings · 35
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10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS
2014 · Benedikt Noethen, Oliver Arnold, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 35
A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications
2017 · Sebastian Haas, Tobias Seifert, et al. · ACM/IEEE Design Automation Conference (DAC) · 33
Nonvolatile Multilevel Resistive Switching in $ \hbox{Ar}^{+}$ Irradiated $\hbox{BiFeO}_{3}$ Thin Films
2012 · Y. Shuai, X. Ou, et al. · IEEE Electron Device Letters · 33
Statistical analysis of analog structures through variance calculation
2002 · A. Graupner, W. Schwarz, et al. · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 33
A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology
2012 · Sebastian Hoppner, Holger Eisenreich, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 31
CMOS image sensor with mixed-signal processor array
2003 · A. Graupner, J. Schreiter, et al. · IEEE Journal of Solid-State Circuits · 28
Replicating experimental spike and rate based neural learning in CMOS
2010 · Christian Mayr, Marko Noack, et al. · IEEE International Symposium on Circuits and Systems proceedings · 27
Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughput
2010 · S. Hartmann, S. Schiefer, et al. · IEEE International Conference on Electronics, Circuits and Systems (ICECS) · 25
A power management architecture for fast per-core DVFS in heterogeneous MPSoCs
2012 · Sebastian Hoppner, Chenming Shao, et al. · IEEE International Symposium on Circuits and Systems proceedings · 24
Works count: 155
Citation count: 2,105
H-index: 24
I10-index: 52
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