Author

Shigeki Wada

Observed institution: NEC (Japan)

OpenAlex ID: A5110050903

A 40-Gb/s CDR Circuit With Adaptive Decision-Point Control Based on Eye-Opening Monitor Feedback

2008 · Hidemi Noguchi, Nobuhide Yoshida, et al. · IEEE Journal of Solid-State Circuits · 34

A 40Gb/s CDR with Adaptive Decision-Point Control Using Eye-Opening-Monitor Feedback

2008 · Hidemi Noguchi, Nobuhide Yoshida, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 11

A 35-to-46-Gb/s Ultra-Low Jitter Clock and Data Recovery Circuit for Optical Fiber Transmission Systems

2007 · Hidemi Noguchi, Kenichi Hosoya, et al. · Technical digest -- IEEE Compound Semiconductor Integrated Circuit Symposium · 4

0.21-fJ GaAs DCFL Circuits Using 0.2-ìm Y-Shaped Gate AIGaAs/InGaAs E/D-HJFETs

1999 · Shigeki Wada, Masatoshi Tokushima, et al.

An Ultra-low Power-consumption High-speed GaAs 256/258 Dual-modulus Prescaler IC

1997 · Tadashi Maeda, Shigeki Wada, et al. · 電子情報通信学会技術研究報告. MW, マイクロ波

Works count: 5

Citation count: 49

H-index: 3

I10-index: 2