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Huiming Bu

The future transistors
2023 · Wei Cao, Huiming Bu, et al. · Nature · 693
Sub- $10^{-9}~\Omega $ -cm2 n-Type Contact Resistivity for FinFET Technology
2016 · Hiroaki Niimi, Zuoguang Liu, et al. · IEEE Electron Device Letters · 62
Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond
2010 · Ali Khakifirooz, Kangguo Cheng, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 40
Bias Temperature Instability Reliability in Stacked Gate-All-Around Nanosheet Transistor
2019 · Miaomiao Wang, Jingyun Zhang, et al. · IEEE International Reliability Physics Symposium proceedings · 37
Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology
2023 · Shogo Mochizuki, Nicolas Loubet, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 29
Aggressively Scaled Strained-Silicon-on-Insulator Undoped-Body High- $\kappa$/Metal-Gate nFinFETs for High-Performance Logic Applications
2011 · Kingsuk Maitra, Ali Khakifirooz, et al. · IEEE Electron Device Letters · 28
Backside Power Distribution for Nanosheet Technologies Beyond 2nm
2024 · Ruilong Xie, Wonhyuk Hong, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 26
Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond
2011 · Chung-Hsun Lin, Wilfried Haensch, et al. · Symposium on VLSI Technology · 24
Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors
2021 · Curtis Durfee, Subhadeep Kal, et al. · ECS Transactions · 17
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High-Performance Partially Depleted SOI PFETs With In Situ Doped SiGe Raised Source/Drain and Implant-Free Extension
2011 · Ali Khakifirooz, Kangguo Cheng, et al. · IEEE Electron Device Letters · 16
Monolithic Stacked FET with Stepped Channels for Future Logic Technologies
2024 · Chen Zhang, SeungMin Song, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 15
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
2017 · Heng Wu, Soon-Cheon Seo, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 15
Leakage aware Si/SiGe CMOS FinFET for low power applications
2018 · Gen Tsutsui, Curtis Durfee, et al. · Symposium on VLSI Technology · 12
SiGe FinFET for practical logic libraries by mitigating local layout effect
2017 · Gen Tsutsui, Huimei Zhou, et al. · Symposium on VLSI Technology · 12
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
2016 · Gen Tsutsui, Ruqiang Bao, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 12
FINFET technology a substrate perspective
2011 · Huiming Bu · IEEE International SOI Conference (SOI) · 10
Low-k spacers for advanced low power CMOS devices with reduced parasitic capacitances
2008 · Elbert Huang, Eric Joseph, et al. · IEEE International SOI Conference (SOI) · 10
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
2019 · Andrew Greene, Huimei Zhou, et al. · Symposium on VLSI Technology · 8
Opportunities and Challenges of FinFET as a Device Structure Candidate for 14nm Node CMOS Technology
2011 · Tenko Yamashita, Veeraraghavan Basker, et al. · ECS Transactions · 7
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Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
2019 · Ruilong Xie, Chanro Park, et al. · Symposium on VLSI Technology · 6
(Invited) Epitaxy of (SiGe/Si) Superlattices for the Fabrication of Horizontal Gate-All-Around Nanosheet Transistors
2018 · Nicolas J Loubet, Juntao Li, et al. · ECS Meeting Abstracts · 5
Ultra-Thin Body and BOX (UTBB) Device for Aggressive Scaling of CMOS Technology
2011 · Qing Liu, Atsushi Yagishita, et al. · ECS Transactions · 5
Extraction of Effective Oxide Thickness for SOI FINFETs With High- $\kappa$/Metal Gates Using the Body Effect
2010 · Sujata Paul, Frank Yeh, et al. · IEEE Electron Device Letters · 5
Parasitic Resistance Reduction for Aggressively Scaled Stacked Nanosheet Transistors
2020 · Su-Chen Fan, Ruilong Xie, et al. · IEEE International Interconnect Technology Conference (IITC) · 4
Challenges and Solutions of Extremely Thin SOI (ETSOI) for CMOS Scaling to 22nm Node and Beyond
2010 · Kangguo Cheng, Ali Khakifirooz, et al. · ECS Transactions · 4
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Works count: 46
Citation count: 1,123
H-index: 12
I10-index: 17
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