Product
Help
Pricing
About
Jobs
Log in
Get started
Work
Add to collection
Low-k spacers for advanced low power CMOS devices with reduced parasitic capacitances
HTML
Details
Locations
Year:
2008
Type:
conference-paper
Source:
IEEE International SOI Conference (SOI)
DOI:
10.1109/soi.2008.4656274
Authors:
Elbert Huang,
Eric Joseph,
Huiming Bu,
Xinlin Wang,
Nicholas Fuller,
Christine Ouyang,
Eva Simonyi,
Hosadurga Shobha,
Tien Cheng,
Anupama Mallikarjunan,
Isaac Lauer,
Sunfei Fang,
Wilfried Haensch,
Chun-Yung Sung,
Sampath Purushothaman,
Ghavam Shahidi
show all 16
Institutions:
IBM (United States),
IBM Research - Thomas J. Watson Research Center
Language:
English
Topic:
Copper Interconnects and Reliability
Subfield:
Electronic, Optical and Magnetic Materials
Field:
Materials Science
Domain:
Physical Sciences
Open Access status:
closed
OpenAlex ID:
W2017430071
FWCI:
Cites:
2
Cited by:
10
Related to:
10