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Jim Tschanz

Observed names: J. Tschanz, J.W. Tschanz, Jim W. Tschanz
OpenAlex ID: A5111484157
Parameter variations and impact on circuits and microarchitecture
2003 · Shekhar Borkar, Tanay Karnik, et al. · ACM/IEEE Design Automation Conference (DAC) · 1,394
Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors
2003 · J.W. Tschanz, S. Narendra, et al. · IEEE Journal of Solid-State Circuits · 130
Variation-tolerant circuits
2005 · Jim Tschanz, Keith Bowman, et al. · ACM/IEEE Design Automation Conference (DAC) · 64
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction
2010 · Arijit Raychowdhury, Bibiche Geuskens, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 63
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor
2010 · S. Dighe, S. Vangal, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 59
Parameter variations and impact on circuits and microarchitecture
2003 · Shekhar Borkar, Tanay Karnik, et al. · ACM/IEEE Design Automation Conference (DAC) · 50
Dynamic-sleep transistor and body bias for active leakage power control of microprocessors
2003 · J. Tschanz, S. Narendra, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 49
20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS
2017 · Harish Kumar Krishnamurthy, Vaibhav Vaidya, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 43
Formal derivation of optimal active shielding for low-power on-chip buses
2006 · M. Ghoneima, Y.I. Ismail, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 43
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors
2002 · T. Karnik, Yibin Ye, et al. · ACM/IEEE Design Automation Conference (DAC) · 37
5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS
2002 · S. Vangal, M.A. Anders, et al. · IEEE Journal of Solid-State Circuits · 35
Leakage and process variation effects in current testing on future CMOS circuits
2002 · A. Keshavarzi, J.W. Tschanz, et al. · IEEE Design & Test of Computers · 34
A 0.45–1V fully integrated reconfigurable switched capacitor step-down DC-DC converter with high density MIM capacitor in 22nm tri-gate CMOS
2013 · Rinkle Jain, Bibiche Geuskens, et al. · Symposium on VLSI Circuits · 28
Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques
2006 · M. Ghoneima, Y.I. Ismail, et al. · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 24
Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design
2009 · Yu Cao, Jim Tschanz, et al. · IEEE Design & Test of Computers · 23
Design for Resilience to Soft Errors and Variations
2007 · Ming Zhang, T.M. Mak, et al. · IEEE International On-Line Testing Symposium (IOLTS) · 22
Dual-V CC 8T-bitcell SRAM array in 22nm tri-gate CMOS for energy-efficient operation across wide dynamic voltage range
2013 · Jaydeep P. Kulkarni, Muhammad Khellah, et al. · Symposium on VLSI Circuits · 18
Comparative performance, leakage power and switching power of circuits in 150 nm PD-SOI and bulk technologies including impact of SOI history effect
2002 · S. Narendra, J. Tschanz, et al. · Symposium on VLSI Circuits · 17
A 22nm dynamically adaptive clock distribution for voltage droop tolerance
2012 · Keith A. Bowman, Carlos Tokunaga, et al. · Symposium on VLSI Circuits · 16
Design for test and reliability in ultimate CMOS
2012 · M. Nicolaidis, L. Anghel, et al. · Design, Automation, and Test in Europe · 12
Minimum supply voltage for sequential logic circuits in a 22nm technology
2013 · Chia-Hsiang Chen, Keith Bowman, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 11
Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops
2011 · Arijit Raychowdhury, Jim Tschanz, et al. · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · 10
A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit
2020 · S. Paul, T. Majumder, et al. · Symposium on VLSI Circuits · 7
A 5.4V-Vin, 9.3A/mm2 10MHz Buck IVR Chiplet in 55nm BCD Featuring Self-Timed Bootstrap and Same-Cycle ZVS Control
2024 · Sally Amin, Harish Krishnamurthy, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 5
Comparative delay, noise and energy of high-performance domino adders with stack node preconditioning (SNP)
2002 · Yibin Ye, J. Tschanz, et al. · Symposium on VLSI Circuits · 4
Works count: 29
Citation count: 2,201
H-index: 17
I10-index: 22
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