Author

Jan A. Peperstraete

Observed names: J. A Peperstraete, J. A. PEPERSTRAETE, J. A. Peperstraete, J. PEPERSTRAETE, J. Peperstraete, J.A. Peperstraete, Jan Peperstraete

Observed institution: KU Leuven

OpenAlex ID: A5111497516

Cycle-static dataflow

1996 · G. Bilsen, M. Engels, et al. · IEEE Transactions on Signal Processing · 519

Cyclo-static data flow

2002 · G. Bilsen, M. Engels, et al. · IEEE International Conference on Acoustics Speech and Signal Processing · 196

Grape-II: a system-level prototyping environment for DSP applications

1995 · R. Lauwereins, M. Engels, et al. · Computer · 157

GRAPE: a CASE tool for digital signal parallel processing

1990 · R. Lauwereins, M. Engels, et al. · IEEE ASSP Magazine · 76

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Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets

1997 · Marleen Adé, Rudy Lauwereins, et al. · ACM/IEEE Design Automation Conference (DAC) · 59

Geometric parallelism and cyclo-static data flow in GRAPE-II

2002 · R. Lauwereins, P. Wauters, et al. · International Workshop on Rapid System Prototyping (RSP) · 47

Static scheduling of multi-rate and cyclo-static DSP-applications

2002 · G. Bilsen, M. Engels, et al. · SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems · 47

Cycle-static dataflow: model and implementation

2002 · M. Engels, G. Bilson, et al. · Asilomar Conference on Signals, Systems and Computers (ACSSC) · 39

Cyclo-dynamic dataflow

2002 · P. Wauters, M. Engels, et al. · Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP) · 37

Buffer memory requirements in DSP applications

2002 · M. Ade, R. Lauwereins, et al. · International Workshop on Rapid System Prototyping (RSP) · 35

Hardware-software codesign with GRAPE

2002 · M. Ade, R. Lauwereins, et al. · International Workshop on Rapid System Prototyping (RSP) · 21

Data Memory Minimisation For Synchronous Data Flow Graphs Emulated On DSP-FPGA Targets

2005 · M. Ade, R. Lauwereins, et al. · ACM/IEEE Design Automation Conference (DAC) · 20

GRAPE-II: a tool for the rapid prototyping of multi-rate asynchronous DSP applications on heterogeneous multiprocessors

2003 · R. Lauwereins, M. Engels, et al. · International Workshop on Rapid System Prototyping (RSP) · 18

Area-Time Performances of Some Neural Computations

1994 · Valeriu Beiu, J.A. Peperstraete, et al. · 18

Rapid prototyping for DSP systems with multiprocessors

1991 · M. Engels, R. Lauwereins, et al. · IEEE Design & Test of Computers · 18

Efficient Decomposition of Comparison and Its Applications

1993 · Valeriu Beiu, J.A. Peperstraete, et al. · The European Symposium on Artificial Neural Networks · 16

Design of a processing board for a programmable multi-VSP system

1993 · M. Engels, R. Lauwereins, et al. · The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology · 13

Analog-to-Digital Conversion Based on a Voltage-to-Frequency Converter

1979 · J. M. Vandeursen, J. A. Peperstraete · IEEE Transactions on Industrial Electronics and Control Instrumentation · 13

Close Approximations of Sigmoid Functions by Sum of Steps for VLSI Implementation of Neural Networks

1994 · Valeriu Beiu, J.A. Peperstraete, et al. · 12

Internal model control with improved disturbance rejection

1995 · J. M. VANDEURSEN, J. A. PEPERSTRAETE · International Journal of Control · 11

Code generation for compiled bit-true simulation of DSP applications

2002 · L. De Coster, M. Ade, et al. · International Symposium on System Synthesis (ISSS) · 10

Survey Of Backward Error Recovery Techniques For Multicomputers Based On Checkpointing And Rollback

1998 · G. Deconinck, J. Vounctx, et al. · International Journal of Modelling and Simulation · 10

Implementing streams on a data flow computer system with paged memory

1983 · L. J. Caluwaerts, J. Debacker, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 9

Model-based and PID controllers for disturbance rejection in processes with time delay: a comparison

1996 · Jean-Marie E. Vandeursen, Jan A. Peperstraete · ISA Transactions · 8

A data flow architecture with a paged memory system

1982 · L. J. Caluwaerts, J. Debacker, et al. · Proceedings - International Symposium on Computer Architecture/Proceedings · 8

Works count: 73

Citation count: 1,502

H-index: 16

I10-index: 22