Author

K. Koyama

Institution: NEC (Japan)

Observed institution: NEC (Japan)

OpenAlex ID: A5111702128

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay

1996 · T. Saeki, Y. Nakaoka, et al. · IEEE Journal of Solid-State Circuits · 87

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

1992 · A. Tanabe, T. Takeshima, et al. · IEEE Journal of Solid-State Circuits · 81

Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention time

2002 · K. Saino, S. Horiba, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 76

A 1-gb/s/pin 512-mb ddrii sdram using a digital dll and a slew-rate-controlled output buffer

2003 · T. Matano, Y. Takai, et al. · IEEE Journal of Solid-State Circuits · 64

A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay

2002 · T. Saeki, Y. Nakaoka, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 35

A 7.68 GIPS 3.84 GB/s 1W parallel image processing RAM integrating a 16 Mb DRAM and 128 processors

2002 · Y. Aimoto, T. Kimura, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 27

A 1-Gb DRAM for file applications

1995 · T. Sugibayashi, I. Naritake, et al. · IEEE Journal of Solid-State Circuits · 26

A 4-level storage 4 Gb DRAM

2002 · T. Murotani, I. Naritake, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 25

A 1 Gb DRAM for file applications

2002 · T. Sugibayashi, I. Naritake, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 23

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

2002 · T. Matano, M. Morino, et al. · Symposium on VLSI Circuits · 14

A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM

1990 · T. Takeshima, M. Takada, et al. · IEEE Journal of Solid-State Circuits · 13

A stacked capacitor with (Ba/sub x/Sr/sub 1-x/)TiO/sub 3/ for 256M DRAM

2002 · K. Koyama, T. Sakuma, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 12

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme

2000 · Y. Takai, M. Fujita, et al. · IEEE Journal of Solid-State Circuits · 12

A boosted dual world-line decoding scheme for 256 Mb DRAMs

2003 · K. Noda, T. Saeki, et al. · Symposium on VLSI Circuits · 11

1G DRAM cell with diagonal bit-line (DBL) configuration and edge operation MOS (EOS) FET

2002 · K. Shibahara, H. Mori, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 11

A 30 ns 64 Mb DRAM with built-in self-test and repair function

2003 · H. Koike, A. Tanabe, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 10

Bipolar transistor fabrication using selective epitaxial growth of P- and B-doped layers in gas-source Si molecular beam epitaxy

1990 · H. Hirayama, K. Koyama, et al. · IEEE Electron Device Letters · 9

A 250 Mb/s 1 Gb double data rate SDRAM with a bi-directional delay and an inter-bank shared redundancy scheme

2003 · Y. Takai, M. Fujita, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 6

A 55 ns 16 Mb DRAM

2003 · T. Takeshima, M. Takada, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 6

Highly reliable MIM capacitor technology using low pressure CVD-WN cylinder storage-node for 0.12 /spl mu/m-scale embedded DRAM

1999 · S. Kamiyama, J.M. Drynan, et al. · Symposium on VLSI Technology · 5

Analysis of Isolation Degradation Induced by Interlayer Material in Capacitor Over Bit-Line (COB) DRAM Cell

1994 · H. Mori, K. Shibahara, et al. · International Conference on Solid State Devices and Materials (SSDM) · 5

Two-dimensional borderless contact pad technology for a 0.135 μm/sup 2/ 4-gigabit DRAM cell

2002 · H. Koga, T. Matsuki, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 4

Separation of intrinsic and parasitic MOSFET parameters using a multiple built-in Kelvin test structure

2002 · N. Kasai, H. Mori, et al. · IEEE International Conference on Microelectronic Test Structures (ICMTS) · 3

A self-aligned contact technology using anisotropical selective epitaxial silicon for giga-bit DRAMs

2002 · H. Hada, T. Tatsumi, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 3

Migration of organic residuals in interlayer oxide to interface

1996 · N. Kodama, H. Mori, et al. · Nuclear Instruments and Methods in Physics Research Section B Beam Interactions with Materials and Atoms · 3

Works count: 31

Citation count: 580

H-index: 12

I10-index: 16