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Ku-Feng Lin

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability
2011 · Shyh-Shyuan Sheu, Meng-Fan Chang, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 246
19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme
2014 · Meng-Fan Chang, Jui-Jen Wu, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 149
A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes
2013 · Meng-Fan Chang, Shyh-Shyuan Sheu, et al. · IEEE Journal of Solid-State Circuits · 101
A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time
2012 · Meng-Fan Chang, Che-Wei Wu, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 85
Inhibition of TDP-43 Aggregation by Nucleic Acid Binding
2013 · Yi-Chen Huang, Ku-Feng Lin, et al. · PLoS ONE · 78
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Binding Mechanism of Nonspecific Lipid Transfer Proteins and Their Role in Plant Defense
2004 · Chao-Sheng Cheng, Dharmaraj Samuel, et al. · Biochemistry · 76
Characterization and Structural Analyses of Nonspecific Lipid Transfer Protein 1 from Mung Bean,
2005 · Ku-Feng Lin, Yu-Nan Liu, et al. · Biochemistry · 60
A Reflow-capable, Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Process
2020 · Yi-Chun Shih, Chia-Fu Lee, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 45
A low store energy, low VDDmin, nonvolatile 8T2R SRAM with 3D stacked RRAM devices for low power mobile applications
2010 · Pi-Feng Chiu, Meng-Fan Chang, et al. · Symposium on VLSI Circuits · 45
Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology
2013 · Hung-Chang Yu, Kai-Chun Lin, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 41
Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub-$\mu$ A Sensing Resolution, and 17.5-nS Read Access Time
2019 · Yi-Chun Shih, Chia-Fu Lee, et al. · IEEE Journal of Solid-State Circuits · 39
Low ${\rm VDDmin}$ Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations
2015 · Meng-Fan Chang, Jui-Jen Wu, et al. · IEEE Journal of Solid-State Circuits · 33
A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro
2013 · Meng-Fan Chang, Che-Wei Wu, et al. · IEEE Journal of Solid-State Circuits · 32
15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 10 12 Write Endurance and Integrated Margin-Expansion Schemes
2024 · Ku-Feng Lin, Hiroki Noguchi, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 23
Molecular basis of tail-anchored integral membrane protein recognition by the cochaperone Sgt2
2021 · Ku-Feng Lin, Michelle Y. Fry, et al. · Journal of Biological Chemistry · 21
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Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time
2018 · Yi-Chun Shih, Chia-Fu Lee, et al. · Symposium on VLSI Circuits · 21
Evaluation of plant non-specific lipid-transfer proteins for potential application in drug delivery
2004 · Chao-Sheng Cheng, Min-Nan Chen, et al. · Enzyme and Microbial Technology · 20
A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications
2010 · Meng-Fan Chang, Shu-Meng Yang, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 19
A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute
2025 · Tsung-Yung Jonathan Chang, Yen-Huei Chen, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 13
Circuit design challenges and trends in read sensing schemes for resistive-type emerging nonvolatile memory
2012 · Meng-Fan Chang, Ku-Feng Lin, et al. · IEEE International Conference on Solid-State and Integrated Circuit Technology · 9
Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements
2010 · Meng-Fan Chang, Shu-Meng Yang, et al. · IEEE Journal of Solid-State Circuits · 6
A 40nm split gate embedded flash macro with flexible 2-in-1 architecture, code memory with 140MHz read speed and data memory with 1M cycles endurance
2017 · Hung-Chang Yu, Ku-Feng Lin, et al. · Symposium on VLSI Circuits · 5
Demonstration of Embedded MRAM with Sub-50 nm MTJ for RAM-Like and MCU Applications
2025 · Yuan-Jen Lee, Chun-Tai Cheng, et al. · IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 3
Characterization and Structural Analyses of Nonspecific Lipid Transfer Protein 1 from Mung Bean
2005 · Ku-Feng Lin, Yu-Nan Liu, et al. · Biochemistry · 3
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140MHz読取速度とデータ記憶1Mサイクル耐久性を有する柔軟な2-in-1構造,コード記憶を有する40nmスプリットゲートに埋め込まれたフラッシュマクロ【Powered by NICT】
2017 · Yu Hung-Chang, Lin Ku-Feng, et al. · IEEE Conference Proceedings
Works count: 27
Citation count: 1,173
H-index: 18
I10-index: 19
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