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Koichi Nose

On-Chip Optical Interconnect
2009 · Keishi Ohashi, Kenichi Nishi, et al. · Proceedings of the IEEE · 235
Optimization of V/sub DD/ and V/sub TH/ for low-power and high-speed applications
2000 · K. Nose, T. Sakurai · Asia and South Pacific Design Automation Conference (ASP-DAC) · 192
A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme
2012 · Takashi Tokairin, Koichi Nose, et al. · Symposium on VLSI Circuits · 115
A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling
2006 · Koichi Nose, Mikihiro Kajita, et al. · IEEE Journal of Solid-State Circuits · 61
Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops
2007 · Toru Nakura, Koichi Nose, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 57
A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect
2010 · Eisuke Saneyoshi, Koichi Nose, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 37
A 1.1V 35μm × 35μm thermal sensor with supply voltage sensitivity of 2°C/10%-supply for thermal management on the SX-9 supercomputer
2008 · Eisuke Saneyoshi, Koichi Nose, et al. · Symposium on VLSI Circuits · 34
A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines
2012 · Yoshifumi Ikenaga, Masahiro Nomura, et al. · IEEE Journal of Solid-State Circuits · 31
A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm 2
2019 · Shunsuke Okumura, Makoto Yabuuchi, et al. · Symposium on VLSI Technology · 25
A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm 2 .
2019 · Okumura Shunsuke, Yabuuchi Makoto, et al. · IEEE Conference Proceedings · 22
Waveguide-Integrated Si Nano-Photodiode with Surface-Plasmon Antenna and its Application to On-chip Optical Clock Distribution
2008 · Junichi Fujikata, Koichi Nose, et al. · Applied Physics Express · 22
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Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session)
2000 · Koichi Nose, Soo-Ik Chae, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 20
Design methodology and optimization strategy for dual-V/sub TH/ scheme using commercially available tools
2001 · M. Hirabayashi, K. Nose, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 18
20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications
2024 · Koichi Nose, Taro Fujii, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 15
A small-delay defect detection technique for dependable LSIs
2008 · Koichiro Noguchi, Koichi Nose, et al. · Symposium on VLSI Circuits · 15
6.3 A 0.5V, 400MHz, VDD-Hopping Processor with Zero-VTH FD-SOI Technology
2003 · Hiroshi Kawaguchi, Kouichi Kanda, et al. · 14
A 2.4GHz ISM-band digital CMOS wireless transceiver with an intra-symbol adaptively intermittent Rx
2007 · Haruya Ishizaki, Koichi Nose, et al. · Symposium on VLSI Circuits · 13
A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2
2019 · Shunsuke Okumura, Makoto Yabuuchi, et al. · Symposium on VLSI Circuits · 12
Skew-Tolerant Global Synchronization Based on Periodically All-in-Phase Clocking for Multi-Core SOC Platforms
2007 · Atsufumi Shibayama, Koichi Nose, et al. · Symposium on VLSI Circuits · 11
An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing
2010 · Yoichi Yoshida, Koichi Nose, et al. · IEEE Journal of Solid-State Circuits · 10
A 0.016 mm$^{2}$, 2.4 GHz RF Signal Quality Measurement Macro for RF Test and Diagnosis
2008 · Koichi Nose, Masayuki Mizuno · IEEE Journal of Solid-State Circuits · 5
LAGS System Using Data/Instruction Grain Power Control
2007 · Makoto Ikeda, Taku Sogabe, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 5
FP 12.4: A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current
1998 · Hiroshi Kawaguchi, Koichi Nose, et al. · 5
Waveguide-integrated Si nano-photodiode with surface-plasmon antenna and its application to on-chip optical clock signal distribution
2008 · Junichi Fujikata, Koichi Nose, et al. · IEEE International Conference on Group IV Photonics (GFP) · 3
Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology
2002 · Koichi Nose, Takayasu Sakurai · International Symposium on Low Power Electronics and Design (ISLPED) · 3
Works count: 42
Citation count: 988
H-index: 15
I10-index: 20
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