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G. H. Ma

Observed name: G. H.
OpenAlex ID: A5111794680
The observation of trapping and detrapping effects in high-k gate dielectric MOSFETs by a new gate current Random Telegraph Noise (IG-RTN) approach
2008 · C. M. Chang, Steve S. Chung, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 63
Strain Effects of Si and SiGe Channel on (100) and (110) Si Surfaces for Advanced CMOS Applications
2007 · W. T. Chiang, J. W. Pan, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 21
A Novel “hybrid” high-k/metal gate process for 28nm high performance CMOSFETs
2009 · C. M. Lai, C. T. Lin, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 12
Mobility and Strain Effects on <110>/(110) SiGe channel pMOSFETs for High Current Enhancement
2006 · J. W. Pan, P. W. Liu, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 11
More strain and less stress- the guideline for developing high-end strained CMOS technologies with acceptable reliability
2008 · Steve S. Chung, E. R. Hsieh, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 7
Optimizing Floating Body Effect & AC performance in 65nm PD-SOI CMOS
2007 · R. M. Huang, T. F. Chen, et al. · IEEE International SOI Conference (SOI) · 4
The Channel Backscattering Characteristics of Sub-100nm CMOS Devices with Different Channel/Substrate Orientations
2007 · Y. J. Tsai, Steve S. Chung, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 4
Technology Roadmaps on the Ballistic Transport in Straln Engineered Nanoscale CMO0S Devices
2007 · Steve S. Chung, Y. J. Tsai, et al. · IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) · 4
Improved Layout Dependence in High Performance SiGe Channel CMOSFETs
2008 · P. W. Liu, W. T. Chiang, et al. · IEEE International Power Modulator Symposium and High-Voltage Workshop (IPMHVC) · 3
The understanding of strain-induced device degradation in advanced MOSFETs with process-induced strain technology of 65nm node and beyond
2010 · M. H. Lin, E. R. Hsieh, et al. · IEEE International Reliability Physics Symposium proceedings · 2
Circuit Performance Optimization in Advanced PD-SOI CMOS Development
2007 · W. T. Chiang, Y. T. Huang, et al. · IEEE International SOI Conference (SOI) · 2
65nm CMOS BULK to SOI comparison
2007 · J.L. Pelloie, Y. Laplanche, et al. · IEEE International SOI Conference (SOI) · 2
A new and simple experimental approach to characterizing the carrier transport and reliability of strained CMOS devices in the quasi-ballistic regime
2009 · E. R. Hsieh, Steve S. Chung, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 1
Dopant and thermal interaction on SPE formed SiC for NMOS performance enhancement
2009 · P. W. Liu, T. F. Kuo, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 1
Schottky Source/Drain CMOS Device Optimization with Dopant-Segregated NiPt Silicide
2008 · Y. T. Huang, P. W. Liu, et al. · IEEE International Power Modulator Symposium and High-Voltage Workshop (IPMHVC) · 1
Optimal PD-SOI Technology for High Performance Applications
2008 · W. T. Chiang, P. W. Liu, et al. · IEEE International Power Modulator Symposium and High-Voltage Workshop (IPMHVC) · 1
Thermal budget optimization on Strained Silicon-On-Insulator (SSOI) CMOS
2008 · R. M. Huang, Y. H. Lin, et al. · IEEE International Power Modulator Symposium and High-Voltage Workshop (IPMHVC) · 1
The Ballistic Transport and Reliability of the SOI and Strained-SOI nMOSFETs with 65nm Node and Beyond Technology
2008 · E. R. Hsieh, Derrick W. Chang, et al. · IEEE International Power Modulator Symposium and High-Voltage Workshop (IPMHVC) · 1
SiGe Channel CMOSFETs Fabricated on (110) Surfaces with TaC/HfO2 Gate Stacks
2007 · P. W. Liu, Y. H. Lin, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 1
The investigation of the stress-induced traps and its correlation to PBTI in high-kdielectrics nMOSFETs by the RTN measurement technique
2010 · C. H. Chang, E. R. Hsieh, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
Carrier Transportation of ALD HfLaO Gate Dielectrics with 0.72 nm EOT
2009 · H. W. Chen, Y. W. Liao, et al. · International Conference on Solid State Devices and Materials (SSDM)
Sub-32nm CMOS technology enhancement for low power applications
2009 · R. M. Huang, P. W. Liu, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
Hot Carrier Reliability of ALD HfSiON Gated MOSFETs with Different Compositions
2008 · H. W. Chen, S. Y. Chen, et al. · ECS Transactions
Interfacial and Electrical Characterization of ALD HfSiON Gated MOSFETs with Different Compositions after Channel Hot-Carrier Stress
2008 · H. W. Chen, S. Y. Chen, et al. · International Conference on Solid State Devices and Materials (SSDM)
New observation of an abnormal leakage current in advanced CMOS devices with short channel lengths down to 50nm and beyond
2008 · E. R. Hsieh, Steve S. Chung, et al. · IEEE Silicon Nanoelectronics Workshop
Works count: 27
Citation count: 142
H-index: 5
I10-index: 4
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