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J. P. Colonna
Observed names:
Colonna, J.-P.,
J P Colonna,
J-P Colonna,
J-P. Colonna,
J. Colonna,
J.-P. Colonna,
J.P. Colonna,
JP. Colonna,
Jean Philippe Colonna,
Jean-Pierre Colonna,
Jp. Colonna
show all 11
Institutions:
Commissariat à l'Énergie Atomique et aux Énergies Alternatives,
Laboratoire d'Électronique des Technologies de l'Information,
Université Grenoble Alpes
Observed institutions:
University of Udine,
Commissariat à l'Énergie Atomique et aux Énergies Alternatives,
CEA Grenoble,
Direction de la Recherche Technologique,
Laboratoire d'Électronique des Technologies de l'Information,
Université Grenoble Alpes
show all 6
OpenAlex ID:
A5111832779
15nm-diameter 3D stacked nanowires with independent gates operation: ΦFET
2008
·
C. Dupre
, A. Hubert
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
126
Deep-UV Lithography Fabrication of Slot Waveguides and Sandwiched Waveguides for Nonlinear Applications
2007
·
E. Jordana
, J.-M. Fedeli
, et al.
·
IEEE International Conference on Group IV Photonics (GFP)
·
53
A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration
2009
·
A. Hubert
, E. Nowak
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
46
Reliability of charge trapping memories with high-k control dielectrics (Invited Paper)
2009
·
G. Molas
, M. Bocquet
, et al.
·
Microelectronic Engineering
·
42
Erbium emission in MOS light emitting devices: from energy transfer to direct impact excitation
2012
·
J M Ramírez
, F Ferrarese Lupi
, et al.
·
Nanotechnology
·
39
Ultra-high four wave mixing efficiency in slot waveguides with silicon nanocrystals
2011
·
A. Trita
, C. Lacava
, et al.
·
Applied Physics Letters
·
34
Comparative Scalability of PVD and CVD TiN on HfO2 as a Metal Gate Stack for FDSOI cMOSFETs down to 25nm Gate Length and Width
2006
·
F. Andrieu
, O. Faynot
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
32
Thorough investigation of Si-nanocrystal memories with high-k interpoly dielectrics for sub-45nm node Flash NAND applications
2007
·
G. Molas
, M. Bocquet
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
31
Er-doped light emitting slot waveguides monolithically integrated in a silicon photonic chip
2013
·
J M Ramírez
, F Ferrarese Lupi
, et al.
·
Nanotechnology
·
29
25nm Short and Narrow Strained FDSOI with TiN/HfO2 Gate Stack
2006
·
S. Deleonibus
, C. Mazure
, et al.
·
Symposium on VLSI Technology
·
29
New insight on the charge trapping mechanisms of SiN-based memory by atomistic simulations and electrical modeling
2009
·
E. Vianello
, L. Perniola
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
28
Localized SOI technology: an innovative Low Cost self-aligned process for Ultra Thin Si-film on thin BOX integration for Low Power applications
2007
·
S. Monfray
, MP. Samson
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
23
New challenges and opportunities for 3D integrations
2015
·
J. Michailos
, P. Coudrain
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
20
Scalability of split-gate charge trap memories down to 20nm for low-power embedded memories
2011
·
L. Masoero
, G. Molas
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
18
Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories
2009
·
M. Bocquet
, G. Molas
, et al.
·
Solid-State Electronics
·
17
Performance and Modeling of Si-Nanocrystal Double-Layer Memory Devices With High- $k$ Control Dielectrics
2012
·
G. Gay
, G. Molas
, et al.
·
IEEE Transactions on Electron Devices
·
14
Evaluation of HfAlO high-k materials for control dielectric applications in non-volatile memories
2008
·
G. Molas
, M. Bocquet
, et al.
·
Microelectronic Engineering
·
13
Coupling of Advanced Optical and Chemical Characterization Techniques for Optimization of High-κ Dielectrics with Nanometer Range Thickness
2007
·
C. Licitra
, E. Martinez
, et al.
·
AIP conference proceedings
·
13
In-depth Investigation of Hf-based High-k Dielectrics as Storage Layer of Charge-Trap NVMs
2006
·
J. Buckley
, M. Bocquet
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
13
3D integration demonstration of a wireless product with design partitioning
2012
·
G. Druais
, P. Ancey
, et al.
·
IEEE International D Systems Integration Conference
·
11
Direct probing of trapped charge dynamics in SiN by Kelvin Force Microscopy
2010
·
E. Vianello
, E. Nowak
, et al.
·
IEEE International Conference on Microelectronic Test Structures (ICMTS)
·
10
Study of parasitic trapping in alumina used as blocking oxide for nonvolatile memories
2011
·
J. P. Colonna
, M. Bocquet
, et al.
·
Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena
·
9
Investigation of the role of H-related defects in Al2O3 blocking layer on charge-trap memory retention by atomistic simulations and device physical modelling
2010
·
G. Molas
, L. Masoero
, et al.
·
Technical digest - International Electron Devices Meeting/Technical digest
·
9
Realization of Hybrid Silicon core/silicon Nitride Shell Nanodots by LPCVD for NVM Application
2008
·
Jean Philippe Colonna
, Gabriel Molas
, et al.
·
MRS Proceedings
·
9
Physical Understanding of Program Injection and Consumption in Ultra-Scaled SiN Split-Gate Memories
2012
·
L. Masoero
, G. Molas
, et al.
·
IEEE International Memory Workshop (IMW)
·
7
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Works count:
54
Citation count:
748
H-index:
15
I10-index:
21
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