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Navin Kumar Mishra

Observed names: N. Mishra, Navin K. Mishra, Navin Mishra
Observed institution: Rambus (United States)
OpenAlex ID: A5111885101
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface
2012 · Kambiz Kaviani, Ting Wu, et al. · IEEE Journal of Solid-State Circuits · 41
Technology and circuit optimization of resistive RAM for low-power, reproducible operation
2014 · D. C. Sekar, B. Bateman, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 28
A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface
2012 · Amir Amirkhany, Jason Wei, et al. · IEEE Journal of Solid-State Circuits · 25
A 12.8-Gb/s/link tri-modal single-ended memory interface for graphics applications
2011 · Amir Amirkhany, J. Wei, et al. · Symposium on VLSI Circuits · 7
A tri-modal 20Gbps/link differential/DDR3/GDDR5 memory interface
2011 · Kambiz Kaviani, Ting Wu, et al. · Symposium on VLSI Circuits · 6
An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface
2011 · Navin K. Mishra, Manish Jain, et al. · Custom Integrated Circuits Conference · 3
A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL
2007 · Vijay Khawshe, Pravin Kumar, et al. · International Conference on VLSI Design · 1
Works count: 7
Citation count: 111
H-index: 5
I10-index: 3
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