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A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface

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Year: 2012
Type: article
Source: IEEE Journal of Solid-State Circuits
DOI: 10.1109/jssc.2012.2185369
Authors: Amir Amirkhany, Jason Wei, Navin Kumar Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan
Institutions: Rambus (United States), Xilinx (United States)
Language: English

Topic: Advancements in PLL and VCO Technologies
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences

Open Access status: closed

Funders: University of Arizona, Technische Universität Berlin, Southeast University
OpenAlex ID: W2019196754
FWCI: 2.401
Cites: 24
Cited by: 25
Related to: 10
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