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Author

R. Kolla

OpenAlex ID: A5111908531
Hierarchical design based on a calculus of nets
1987 · B. Becker, G. Hotz, et al. · ACM/IEEE Design Automation Conference (DAC) · 33
A dynamic programming approach to the power supply net sizing problem
2002 · R. Kolla · European Design Automation Conference · 9
Spanning tree based state encoding for low power dissipation
2003 · W. Noth, R. Kolla · Design, Automation, and Test in Europe · 8
A graphical system for hierarchical specifications and checkups of VLSI circuits
1990 · Bernd Becker, T. Burch, et al. · European Design Automation Conference · 8
A graphical system for hierarchical specifications and checkups of VLSI circuits
2002 · B. Becker, T. Burch, et al. · European Design Automation Conference · 6
A cell-based approach to performance optimization of fanout-free circuits
1992 · U. Hinsberger, R. Kolla · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 6
TROY: a tree based approach to logic synthesis and technology mapping
2002 · W. Noth, U. Hinsberger, et al. · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 4
Optimal technology mapping for single output cells
2002 · U. Hinsberger, R. Kolla · ACM Great Lakes Symposium on VLSI (GLSVLSI) · 4
Cell based performance optimization of combinational circuits
2002 · U. Hinsberger, R. Kolla · European Design Automation Conference · 3
Boolean matching for large libraries
2002 · U. Hinsberger, R. Kolla · ACM/IEEE Design Automation Conference (DAC) · 3
Node normalization and decomposition in low power technology mapping
2002 · W. Noth, R. Kolla · International Symposium on Low Power Electronics and Design (ISLPED) · 1
Disproving the perfect-rate property of data-flow graphs unfolded by the least common multiple of the number of loop registers
2003 · F. Wolz, R. Kolla · IEEE Transactions on Computers
Works count: 13
Citation count: 85
H-index: 6
I10-index: 1
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