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Bipul C. Paul

Observed names: B Paul., B. C. Paul, B. Paul, B.C. Paul, Bipul Chandra Paul, Bipul Paul
Observed institutions: Toshiba (Japan), Purdue University West Lafayette, GlobalFoundries (United States), Toshiba (United States), Stanford SystemX Alliance, Indian Institute of Science Bangalore, Stanford University
OpenAlex ID: A5111972172
Circuit Failure Prediction and Its Application to Transistor Aging
2007 · Mridul Agarwal, Bipul C. Paul, et al. · IEEE VLSI Test Symposium (VTS) · 455
Impact of NBTI on the temporal performance degradation of digital circuits
2005 · B.C. Paul, Kunhyuk Kang, et al. · IEEE Electron Device Letters · 293
Robust subthreshold logic for ultra-low power operation
2001 · H. Soeleman, K. Roy, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 286
Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices
2005 · A. Bansal, B.C. Paul, et al. · IEEE Transactions on Electron Devices · 209
A process-tolerant cache architecture for improved yield in nanoscale technologies
2005 · A. Agarwal, B.C. Paul, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 196
A 1 GHz Integrated Circuit with Carbon Nanotube Interconnects and Silicon Transistors
2008 · Gael F. Close, Shinichi Yasuda, et al. · Nano Letters · 192
Process variation in embedded memories: failure analysis and variation aware architecture
2005 · A. Agarwal, B.C. Paul, et al. · IEEE Journal of Solid-State Circuits · 173
Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits
2006 · B.C. Paul, Kunhyuk Kang, et al. · Design, Automation, and Test in Europe · 149
Fully Integrated Graphene and Carbon Nanotube Interconnects for Gigahertz High-Speed CMOS Electronics
2010 · Xiangyu Chen, Deji Akinwande, et al. · IEEE Transactions on Electron Devices · 147
Novel sizing algorithm for yield improvement under process variation in nanometer technology
2004 · Seung Hoon Choi, Bipul C. Paul, et al. · ACM/IEEE Design Automation Conference (DAC) · 142
Optimized Circuit Failure Prediction for Aging: Practicality and Promise
2008 · M. Agarwal, V. Balakrishnan, et al. · IEEE International Test Conference (ITC) · 141
An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping
2006 · Aditya Bansal, Bipul C. Paul, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 140
Impact of a Process Variation on Nanowire and Nanotube Device Performance
2007 · B.C. Paul, S. Fujita, et al. · IEEE Transactions on Electron Devices · 110
Device Optimization for Digital Subthreshold Logic Operation
2005 · B.C. Paul, A. Raychowdhury, et al. · IEEE Transactions on Electron Devices · 106
Contact engineering for organic semiconductor devices via Fermi level depinning at the metal-organic interface
2010 · Zihong Liu, Masaharu Kobayashi, et al. · Physical Review B · 89
Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits
2007 · Bipul C. Paul, Kunhyuk Kang, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 80
Impact of Process Variation on Nanowire and Nanotube Device Performance
2007 · B. C. Paul, S. Fujita, et al. · Conference digest · 77
Robust ultra-low power sub-threshold DTMOS logic
2000 · H. Soeleman, K. Roy, et al. · International Symposium on Low Power Electronics and Design (ISLPED) · 61
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Underlap DGMOS for digital-subthreshold operation
2006 · B.C. Paul, A. Bansal, et al. · IEEE Transactions on Electron Devices · 60
Modeling and analysis of circuit performance of ballistic CNFET
2006 · B.C. Paul, S. Fujita, et al. · ACM/IEEE Design Automation Conference (DAC) · 58
Statistical Timing Analysis using Levelized Covariance Propagation
2005 · Kunhyuk Kang, B.C. Paul, et al. · Design, Automation, and Test in Europe · 56
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation
2005 · A. Raychowdhury, B.C. Paul, et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 54
Low-power design techniques for scaled technologies
2005 · Bipul C. Paul, Amit Agarwal, et al. · Integration · 49
Monolithic Integration of CMOS VLSI and Carbon Nanotubes for Hybrid Nanotechnology Applications
2008 · D. Akinwande, S. Yasuda, et al. · IEEE Transactions on Nanotechnology · 48
Impact of gate underlap on gate capacitance and gate tunneling current in 16 nm DGMOS devices
2005 · A. Bansal, B.C. Paul, et al. · IEEE International SOI Conference (SOI) · 45
Works count: 77
Citation count: 3,986
H-index: 30
I10-index: 46
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