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Author

A. Kaneko

Institution: Toshiba (Japan)
Observed institutions: Toshiba (Japan), Fujitsu (Japan)
OpenAlex ID: A5113485439
Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length
2006 · K. Okano, T. Izumida, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 78
Effects of nitrogen in HfSiON gate dielectric on the electrical and thermal characteristics
2003 · M. Koyama, A. Kaneko, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 76
High-Performance FinFET with Dopant-Segregated Schottky Source/Drain
2006 · A. Kaneko, A. Yagishita, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 55
Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension
2006 · A. Kaneko, A. Yagishita, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 46
Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond
2006 · H. Kawasaki, K. Okano, et al. · Symposium on VLSI Technology · 45
Careful examination on the asymmetric Vfb shift problem for poly-Si/HfSiON gatestack and its solution by the Hf concentration control in the dielectric near the poly-Si interface with small EOT expense
2005 · M. Koyama, Y. Kamimuta, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 27
Nitrogen profile control by plasma nitridation technique for poly-Si gate HfSiON CMOSFET with excellent interface property and ultra-low leakage current
2004 · K. Sekine, S. Inumiya, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 25
Fabrication of HfSiON gate dielectrics by plasma oxidation and nitridation, optimized for 65 nm mode low power CMOS applications
2004 · S. Inumiya, K. Sekine, et al. · Symposium on VLSI Technology · 21
FinFET: the prospective multi-gate device for future SoC applications
2006 · S. Inaba, K. Okano, et al. · European Solid-State Circuits Conference (ESSCIRC) · 13
Improvement of Drive Current in Bulk-FinFET using Full 3D Process/Device Simulations
2006 · T. Kanemura, T. Izumida, et al. · International Conference on Simulation of Semiconductor Processes and Devices · 10
FinFET Process and Integration Technology for High Performance LSI in 22 nm node and beyond
2007 · H. Kawasaki, S. Inaba, et al. · International Workshop on Junction Technology · 9
FinFET: the prospective multi-gate device for future SoC applications
2006 · S. Inaba, K. Okano, et al. · European Solid-State Device Research Conference · 9
A 45k HEMT Gate Array With 35ps DCFL And 50ps BDCFL Gates
1991 · S. Notomi, T. Kondo, et al. · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · 4
HfSiON gate dielectric for CMOS applications
2003 · M. Takayanagi, T. Watanabe, et al. · International Workshop on Gate Insulator (IWGI) · 3
Electricaland Structural Characteristics Of Ultra-Thin TiO2/Ti-Si-O Stacked Gate Insulator Formed by Rf Sputtering Technique
2001 · M. Koyama, A. Kaneko, et al. · MRS Proceedings · 1
Bottom-La Inserted HfSiON Gate Dielectrics with MOCVD HfCN Metal Gate Electrode Realizing High Mobility and Reliability Improvement
2009 · S. Inumiya, A. Kaneko, et al. · International Conference on Solid State Devices and Materials (SSDM)
Works count: 16
Citation count: 422
H-index: 10
I10-index: 10
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