Work

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

Year: 2006

Type: conference-paper

Source: Technical digest - International Electron Devices Meeting/Technical digest

DOI: 10.1109/iedm.2005.1609454

Authors: K. Okano, T. Izumida, H. Kawasaki, A. Kaneko, A. Yagishita, T. Kanemura, M. Kondo, S. Ito, N. Aoki, K. Miyano, T. Ono, K. Yahashi, K. Iwade, T. Kubota, T. Matsushita, I. Mizushima, S. Inaba, K. Ishimaru, K. Suguro, K. Eguchi, Y. Tsunashima, H. Ishiuchi

Institution: Toshiba (Japan)

Language: English

Topic: Advancements in Semiconductor Devices and Circuit Design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W2542396569

FWCI: 8.44

Cites:

Cited by: 78

Related to: 10