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Wei Yip Loh

Prospect of tunneling green transistor for 0.1V CMOS
2010 · Chenming Hu, Pratik Patel, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 112
Impact of interfacial layer control using Gd2O3 in HfO2 gate dielectric on GaAs
2007 · Goutam Kumar Dalapati, Yi Tong, et al. · Applied Physics Letters · 67
Wide $V_{\rm fb}$ and $V_{\rm th}$ Tunability for Metal-Gated MOS Devices With HfLaO Gate Dielectrics
2007 · X. P. Wang, H. Y. Yu, et al. · IEEE Electron Device Letters · 57
First Demonstration of Monolithic CFET Inverter at 48nm Gate Pitch Toward Future Logic Technology Scaling
2024 · S. Liao, L. Yang, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 45
STLM: A Sidewall TLM Structure for Accurate Extraction of Ultralow Specific Contact Resistivity
2013 · Kausik Majumdar, Saikumar Vivekanand, et al. · IEEE Electron Device Letters · 22
Charge Trapping and Breakdown Mechanism in HfAlO/TaN Gate Stack Analyzed Using Carrier Separation
2004 · W.-Y. Loh, B.J. Cho, et al. · IEEE Transactions on Device and Materials Reliability · 17
Analysis of charge trapping and breakdown mechanism in high-k dielectrics with metal gate electrode using carrier separation
2004 · Wei Yip Loh, Byung Jin Cho, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 17
Integration of GaAs epitaxial layer to Si-based substrate using Ge condensation and low-temperature migration enhanced epitaxy techniques
2007 · Hoon Jung Oh, Kyu Jin Choi, et al. · Journal of Applied Physics · 16
Impact of decoupled plasma nitridation of ultra-thin gate oxide on the performance of p-channel MOSFETs
2002 · Chun Meng Lek, Byung Jin Cho, et al. · Semiconductor Science and Technology · 12
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SiGe CMOS on (110) channel orientation with mobility boosters : Surface orientation, channel directions, and uniaxial strain
2010 · J. Oh, S.-H. Lee, et al. · Symposium on VLSI Technology · 11
Widely Tunable Work Function TaN/Ru Stacking Layer on HfLaO Gate Dielectric
2008 · X. P. Wang, M.-F. Li, et al. · IEEE Electron Device Letters · 9
Temperature programmed decomposition (TPDE) of [Mo(CO)6] on metal oxide supports: a novel tool to elucidate surface acidity and surface-mediated reactions
1998 · W Loh · Talanta · 9
Work function engineering in silicides: Chlorine doping in NiSi
2011 · Alexander Slepko, Alexander A. Demkov, et al. · Journal of Applied Physics · 8
Correlation between interface traps and gate oxide leakage current in the direct tunneling regime
2002 · Wei Yip Loh, Byung Jin Cho, et al. · Applied Physics Letters · 8
Evolution of quasi-breakdown in thin gate oxides
2002 · Wei Yip Loh, Byung Jin Cho, et al. · Journal of Applied Physics · 8
VLSI processed InGaAs on Si MOSFETs with thermally stable, self-aligned Ni-InGaAs contacts achieving: Enhanced drive current and pathway towards a unified contact module
2013 · Rinus T. P. Lee, R. J. W. Hill, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 7
Contact resistance reduction to FinFET source/drain using dielectric dipole mitigated Schottky barrier height tuning
2010 · B. E. Coss, C. Smith, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 6
High Specific Contact Resistance of Ohmic Contacts to n-Ge Source/Drain and Low Transport Characteristics of Ge nMOSFETs
2010 · J. Oh, J. Huang, et al. · International Conference on Solid State Devices and Materials (SSDM) · 5
(Invited) Technology Options to Reduce Contact Resistance in Nanoscale III-V MOSFETs
2015 · Rinus T.P. Lee, Wei Yip Loh, et al. · ECS Transactions · 4
Dual metal gate process by metal substitution of dopant-free polysilicon on high-K dielectric
2005 · Chang Seo Park, Byung Jin Cho, et al. · Symposium on VLSI Technology · 4
Ultra low contact resistivity (< 1×10−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III–V fin TLM structure fabricated with III–V on Si substrates
2014 · Rinus T.P. Lee, Y. Ohsawa, et al. · Technical digest - International Electron Devices Meeting/Technical digest · 3
CMOS Scaling with III-V Channels for Improved Performance and Low Power
2011 · Richard J. Hill, Jungwoo Oh, et al. · ECS Transactions · 2
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Localized oxide degradation in ultrathin gate dielectric and its statistical analysis
2003 · Wei Yip Loh, Byung Jin Cho, et al. · IEEE Transactions on Electron Devices · 2
(Invited) Integration Challenges of III-V Materials in Advanced CMOS Logic
2012 · Richard J. Hill, Jeff Huang, et al. · ECS Transactions · 1
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High temperature millisecond silicide anneal for contact resistivity < 10−8 Ωcm2
2011 · W.-Y Loh, Y. R. Yang, et al. · International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) · 1
Works count: 41
Citation count: 456
H-index: 10
I10-index: 10
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