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Veeresh Kumasigi

Observed names: K. Veeresh, Kumasigi, Veeresh, Veeresh K
ORCID: 0009-0009-8407-1845
Observed ORCID: 0009-0009-8407-1845
OpenAlex ID: A5143617138
Design of Hybrid Full Adder/Subtractor Using Reversible Logic
2026 · K. Veeresh, Vilaskumar Patil · Lecture notes in electrical engineering
A Hardware-Efficient LUT Optimized Fault-Tolerant Reversible 64-bit Arithmetic Processor with Self-Error Correction
2026 · Veeresh K, Vilaskumar Patil · Journal of VLSI Circuits and Systems
Implementation of High-Speed Approximate Adiabatic Logic Using Lector Approach for Security Enhancement
2022 · Dhoni, Vikram, Patil, Vilaskumar, et al. · Zenodo (CERN European Organization for Nuclear Research)
Works count: 3
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