Author

B Jarvis

Institution: REVA University

Observed institution: REVA University

OpenAlex ID: A5147149753

Design of a Low Power Static Random Access Memory (SRAM) with Integration of Clock Gating Technique using 22nm of CMOS Technology

2026 · P. Ranjithkumar, B Jarvis, et al. · International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE)

Works count: 1

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