Design of a Low Power Static Random Access Memory (SRAM) with Integration of Clock Gating Technique using 22nm of CMOS Technology
Year: 2026
Type: conference-paper
Abstract: This paper presents an evaluation of a 6T SRAM cell design utilizing a D flip-flop with an AND gate-based clock gating technique, offering superior power efficiency compared to traditional designs. The proposed design achieves an average power consumption of just $\mathbf{3 5 2. 9 2 n W}$, a remarkable reduction compared to the $112.90 \mu \mathrm{~W}$ consumed by traditional circuits. Additionally, the design using a D flip-flop with a NAND gate-based clock gating technique consumes $576.55 \mu \mathrm{~W}$. The AND gate-based clock gating Mechanism optimizes power consumption by approximately 99.687%, while the NAND gate-based version achieves a reduction of 99.489%, highlighting the substantial impact of these techniques on power efficiency. These results emphasize the potential of clock gating techniques in advancing low power circuit designs.
Authors: P. Ranjithkumar, B Jarvis, Prasenjit Deb, M P Tejas
Institution: REVA University
Language: English
Subfield: Electrical and Electronic Engineering
Field: Engineering
Domain: Physical Sciences
Open Access status: hybrid
OpenAlex ID: W7203470735