Author

S. Vasantha Kumar

Institution: Sengunthar Engineering College (Autonomous)

Observed institution: Sengunthar Engineering College (Autonomous)

OpenAlex ID: A5149977293

Design and FPGA implementation of reversible vedic multipliy and accumulate unit for cryptography applications

2026 · V. Thamizharasan, A. Nikhil, et al. · Analog Integrated Circuits and Signal Processing

Works count: 1

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