Keyword

test pattern generation

Description: A digital circuit testing method that creates input patterns to detect faults or verify the behavior of logic circuits.

Primary topic: VLSI and Analog Circuit Testing (83%)

OpenAlex ID: keywords/test-pattern-generation

GRASP - A New Search Algorithm for Satisfiability

1996 · Joso L Marques Silva · 869

Test pattern generation using Boolean satisfiability

1992 · T. Larrabee · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 703

RT-level ITC'99 benchmarks and first ATPG results

2000 · F. Corno, M.S. Reorda, et al. · IEEE Design & Test of Computers · 542

HITEC: a test generation package for sequential circuits

2002 · T. Niermann, J.H. Patel · 522

MERO: A Statistical Approach for Hardware Trojan Detection

2009 · Rajat Subhra Chakraborty, Francis Wolff, et al. · Lecture notes in computer science · 479

Built-In Self-Test Techniques

1985 · Edward McCluskey · IEEE Design & Test of Computers · 420

Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers

1995 · S. Hellebrand, J. Rajski, et al. · IEEE Transactions on Computers · 408

Transition Fault Simulation

1987 · John Waicukauski, Eric Lindbloom, et al. · IEEE Design & Test of Computers · 402

GRASP-A new search algorithm for satisfiability

2002 · J.P. Marques Silva, K.A. Sakallah · International Conference on Computer Aided Design · 400

Logic Testing and Design for Testability

1985 · Hideo Fujiwara · The MIT Press eBooks · 358

On the generation of test patterns for combinational circuits

1993 · Sarita Thakar · VTechWorks (Virginia Tech) · 349

PDF

A Deductive Method for Simulating Faults in Logic Circuits

1972 · D.B. Armstrong · IEEE Transactions on Computers · 303

Evaluation and improvement of Boolean comparison method based on binary decision diagrams

2003 · M. Fujita, H. Fujisawa, et al. · International Conference on Computer Aided Design · 269

Compactest: a Method to Generate Compact Test Sets for Combinational Circuits

2005 · I. Pomeranz, L.N. Reddy, et al. · Proceedings/Proceedings - International Test Conference · 261

Verification Testing—A Pseudoexhaustive Test Technique

1984 · McCluskey · IEEE Transactions on Computers · 224

Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization

1994 · W. Kunz, D.K. Pradhan · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 214

COMPACTEST: a method to generate compact test sets for combinational circuits

1993 · I. Pomeranz, L.N. Reddy, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 213

Bit-flipping BIST

1996 · Hans-Joachim Wunderlich, Gundolf Kiefer · International Conference on Computer Aided Design · 208

Test generation for sequential circuits

1988 · H.-K.T. Ma, S. Devadas, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 203

Logic design verification via test generation

1988 · M.S. Abadir, J. Ferguson, et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 198

CMOS bridging fault detection

2002 · T.M. Storey, W. Maly · Proceedings/Proceedings - International Test Conference · 183

The Weighted Random Test-Pattern Generator

1975 · H.D. Schnurmann, E. Lindbloom, et al. · IEEE Transactions on Computers · 177

Chapter 2 Satisfiability Solvers

2008 · Carla P. Gomes, Henry Kautz, et al. · Foundations of artificial intelligence · 176

Bit-flipping BIST

2002 · H.-J. Wunderlich, G. Kiefer · International Conference on Computer Aided Design · 176

A method for generating weighted random test patterns

1989 · J. A. Waicukauski, E. Lindbloom, et al. · IBM Journal of Research and Development · 172

Works count: 3,845

Citation count: 33,210