Work

Timing analysis of combinational circuits including capacitive coupling and statistical process variation

Year: 2002

Type: conference-paper

Source: IEEE VLSI Test Symposium (VTS)

DOI: 10.1109/vtest.2000.843826

Authors: B. Choi, D.M.H. Walker

Institutions: Intel (United States), Texas A&M University

Language: English

Topic: Low-power high-performance VLSI design

Subfield: Electrical and Electronic Engineering

Field: Engineering

Domain: Physical Sciences

Open Access status: closed

OpenAlex ID: W1925000611

FWCI: 5.256

Cites: 31

Cited by: 29

Related to: 10